Programmable integrated passive devices

Abstract

An integrated passive device array structure with a value that is programmable during manufacturing. The device structure includes a substantially conductive first layer having a plurality of passive device array elements of the integrated passive device array structure disposed above the substantially conductive first layer. The device further includes an insulating layer formed above the plurality of passive device array elements. One or more vias are selectively formed in the insulating layer. The vias facilitate electrical connections between selected ones of the plurality of passive device array elements with a substantially conductive second layer subsequently deposited above the insulating layer.

What is claimed is:  
     
         1 . An integrated programmable passive device array structure, comprising: 
 a first node;    a plurality of passive device array elements electrically coupled to said first node; and    a second node, said second node being electrically coupled, in a selective manner, to selected ones of said plurality of passive device array elements, said selected ones of said plurality of passive device array elements representing a subset of said plurality of passive device array elements, wherein a value of said programmable passive device array structure is substantially determined by an aggregate of values of said selected ones of said plurality of passive device array elements.    
     
     
         2 . The integrated programmable passive device array structure of    claim 1    wherein said selected ones of said plurality of passive device array elements are configured to be electrically coupled in parallel between said first node and said second node.  
     
     
         3 . The integrated programmable passive device array structure of    claim 1    wherein values of individual passive device array elements of said selected ones of said plurality of passive device array elements are related in a binary manner.  
     
     
         4 . The integrated programmable passive device array structure of    claim 1    wherein said plurality of passive array elements represent capacitors.  
     
     
         5 . The integrated programmable passive device array structure of    claim 4    wherein said first node is implemented in a substantially conductive first layer, said second node being implemented in a substantially conductive second layer above said substantially conductive first layer.  
     
     
         6 . The integrated programmable passive device array structure of    claim 5    wherein each of said plurality of passive device array elements includes a dielectric portion formed of a layer of dielectric material, said layer of dielectric material being disposed between said substantially conductive first layer and said substantially conductive second layer.  
     
     
         7 . The integrated programmable passive device array structure of    claim 6    wherein said layer of dielectric material is separated from said substantially conductive second layer by an insulating layer, each of said selected ones of said plurality of passive device array elements being furnished with a via through said insulating layer to permit said second node to form an electrical contact with said each of said selected ones of said plurality of passive device array elements through said insulating layer.  
     
     
         8 . The integrated programmable passive device array structure of    claim 1    wherein at least one of said plurality of passive device array elements is selected to be electrically decoupled from said second node.  
     
     
         9 . An integrated programmable passive device array structure, comprising: 
 a first node;    a plurality of passive device array elements electrically coupled to said first node, each of said plurality of passive device array elements having a value; and    a second node, said second node being electrically coupled, in a selective manner, to selected ones of said plurality of passive device array elements, said selected ones of said plurality of passive device array elements representing a subset of said plurality of passive device array elements, wherein a value of said programmable passive device array structure is substantially determined by an aggregate of said values of said selected ones of said plurality of passive device array elements.    
     
     
         10 . The integrated programmable passive device array structure of    claim 9    wherein said selected ones of said plurality of passive device array elements are configured to be electrically coupled in parallel between said first node and said second node.  
     
     
         11 . The integrated programmable passive device array structure of    claim 9    wherein the values of said plurality of passive device array elements are related by a predetermined relationship.  
     
     
         12 . The integrated programmable passive device array structure of    claim 11    wherein said predetermined relationship is selected from the group consisting of: binary, linear, geometric, logarithmic, exponential, and arbitrary.  
     
     
         13 . The integrated programmable passive device array structure of    claim 9    wherein at least one of said plurality of passive device array elements is selected from the group consisting of: capacitor, resistor, and inductor.  
     
     
         14 . An integrated circuit device incorporating a programmable capacitor array including a plurality of capacitors, the array comprising: 
 a substrate;    a plurality of bottom capacitor plates disposed on an upper surface of said substrate;    a corresponding plurality of top capacitor plates disposed over said plurality of bottom capacitor plates;    a dielectric disposed between said plurality of bottom capacitor plates and said corresponding plurality of top capacitor plates;    electrical separation means disposed on at least a portion of said corresponding plurality of top capacitor plates, said electrical separation means for electrically separating individual ones of said capacitors; and    a conductive layer applied over said electrical separation means.    
     
     
         15 . The integrated circuit device of    claim 14    wherein said array further comprises an epitaxial layer disposed between said substrate and at least a portion of said plurality of bottom capacitor plates.  
     
     
         16 . The integrated circuit device of    claim 14    wherein said array further comprises a passivation layer deposited on at least a portion of an upper surface of said conductive layer.  
     
     
         17 . The integrated circuit device of    claim 14    further comprising: 
 said electrical separation means formed as a layer of intermediate oxide defining at least one contact hole therethrough, said contact hole being disposed over a selected one of said plurality of top plates; and  
 said conductive layer further defines an electrical path through said contact hole and to said selected one of said plurality of top plates.  
 
     
     
         18 . The integrated circuit device of    claim 17    wherein said layer of intermediate oxide defining at least one contact hole therethrough is formed by a process comprising the steps of: 
 masking at least a portion of said layer of intermediate oxide; and  
 etching at least another portion of said layer of intermediate oxide.  
 
     
     
         19 . The integrated circuit device of    claim 18    wherein said masking step is performed utilizing a process selected from the group consisting of: contact masking, metal masking, via masking, poly masking, and active masking.  
     
     
         20 . The integrated circuit device of    claim 14    further comprising at least one field oxide element disposed between and separating adjacent ones of said plurality of bottom capacitor plates.  
     
     
         21 . The integrated circuit device of    claim 20    wherein at least one of said field oxide element and said plurality of bottom plates is formed by the process consisting of the steps of: 
 masking at least a portion of said at least one of said field oxide and said plurality of bottom plates; and  
 etching at least another portion of said field oxide and said plurality of bottom plates.