Semiconductor device having a shallow trench isolation structure and a method for fabricating the same

Abstract

A semiconductor device having a shallow trench isolation structure, where the upper part of the trench is broader than the lower part of it, comprises an insulating layer on the sidewalls of the upper part of the trench, another insulating layer buried in the trench for isolating semiconductor devices and low-concentration doped regions near the upper part of the trench and high-concentration doped regions near the lower part of the trench. Therefore, the leakage current is prevented due to the sufficient amount of the ions in the high-concentration doped regions near the lower part of the trench and the narrow width effect is minimized owing to the insulating layer on the sidewalls of the upper part of the trench.

What is claimed is:  
     
         1 . A method for fabricating a semiconductor device comprising the steps of: 
 forming a first recess by etching a semiconductor substrate to a predetermined depth;    forming first insulating layer patterns on the sidewalls of said first recess, exposing the bottom of said first recess;    forming a second recess by etching a region not covered with said first insulating layer patterns in said first recess;    forming an ion-doped region in said first and said second recesses by a channel stop ion implantation process; and    forming a second insulating layer with which said first and second recesses are fully filled.    
     
     
         2 . A method in accordance with    claim 1   , whererin said ion-doped region is formed by an oblique ion implantation process.  
     
     
         3 . A method in accordance with    claim 1   , wherein said step of forming said first insulating layer comprises the steps of: 
 forming an insulating layer on the resulting structure; and    applying an isotropic etching process to said insulating layer.    
     
     
         4 . A method in accordance with    claim 1   , wherein said method further comprises the step of forming a third insulating layer on the resulting structure including said first and second recesses to prevent said semiconductor substrate from being damaged during said channel stop ion implantation process.  
     
     
         5 . A method in accordance with    claim 1   , wherein said ion-doped region comprises a low concentration doped region near said first recess and a high concentration doped region near said second recess.  
     
     
         6 . A method for fabricating a semiconductor device having a shallow trench isolation structure including the steps of: 
 forming mask patterns on a semiconductor substrate, exposing a portion of said semiconductor substrate;    selectively etching an exposed region of said semiconductor substrate to a predetermined depth so as to form a first recess;    forming ion-implantation buffer layers on the sidewalls of said first recess, exposing a bottom of said first recess;    etching said semiconductor substrate using said mask patterns and said ion-implantation buffer layers as an etching mask, thereby forming a second recess;    implanting ions into said semiconductor substrate around said first and second recesses, wherein the ions are implanted obliquely; and    forming an insulating layer on the resulting structure and etching back said insulating layer so that said first and second recesses are fully filled with said insulating layer.    
     
     
         7 . A method in accordance with    claim 6   , wherein said method further comprises the step of forming a passivation layer to prevent said semiconductor substrate from being damaged in said ion-implantation process.  
     
     
         8 . A method in accordance with    claim 6   , wherein said mask patterns are made of an oxide layer and a silicon nitride layer deposited, in order, on said semiconductor substrate.  
     
     
         9 . A method in accordance with    claim 6   , wherein said mask patterns are formed by the device isolation masking process and the etching process.  
     
     
         10 . A method in accordance with    claim 6   , wherein said step of forming ion-implantation buffer layer further comprises the steps of: 
 forming an insulating layer on a resulting structure; and    anisotropically etching said insulating layer.    
     
     
         11 . A method in accordance with    claim 6   , wherein said ion-implantation buffer layer is one of, a silicon oxide layer or a silicon nitride layer.  
     
     
         12 . A method in accordance with    claim 6   , wherein said passivation layer is an oxide layer.  
     
     
         13 . A method in accordance with    claim 6   , wherein said etching process is carried out by a chemical-mechanical polishing method.  
     
     
         14 . A semiconductor device having a shallow trench isolation structure comprising: 
 a semiconductor substrate having a trench, wherein the upper part of said trench is broader than the lower part of said trench;    a first insulating layer formed on the sidewalls of said upper part of said trench;    a second insulating layer buried in said trench for isolation of said semiconductor devices; and    low-concentration doped regions formed in said semiconductor device, wherein said low-concentration doped regions are near said upper part of said trench; and    high-concentration doped regions formed in said semiconductor device, wherein said high-concentration doped regions are near said lower part of said trench.    
     
     
         15 . A semiconductor device according to the    claim 14   , wherein said semiconductor device further comprises a third insulating layer formed on the sidewalls of said first insulating layer and said lower part of said trench.  
     
     
         16 . A semiconductor device according to the    claim 14   , wherein said first insulating layer is one of, a silicon oxide layer or a silicon nitride layer.  
     
     
         17 . A method in accordance with    claim 1   , wherein said second insulating layer is silicon oxide layer.  
     
     
         18 . A method in accordance with    claim 15   , wherein said third insulating layer is silicon oxide layer.