Method and device to increase latch-up immunity in cmos device

Abstract

The preferred embodiment of the present invention overcomes the imitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by reducing the mobility of carriers between the devices. The preferred embodiment uses an implant formed beneath trench isolation between n-channel and p-channel devices. This implant preferably comprises relatively large/heavy elements implanted into the wafer beneath the trench isolation. The implant elements reduce the mobility of the charge carriers. This increases the latch-up holding voltage and thus reduces the likelihood of latch-up. The implants can be formed without the need for additional photolithography masks.

1 . An isolation structure for increasing the latch-up holding voltage in a CMOS device fabricated in a semiconductor substrate, the isolation structure comprising: 
 a) a shallow trench fabricated in said semiconductor substrate; and    b) an implant, said implant formed below said trench in said semiconductor substrate, said implant reducing the mobility of carriers in said substrate beneath said shallow trench.    
     
     
         2 . The isolation structure of    claim 1    wherein said implant comprises n-type and p-type species and results in low net dopant profile change.  
     
     
         3 . The isolation structure of    claim 1    wherein said implant comprises an electrically neutral species.  
     
     
         4 . The isolation structure of    claim 1    wherein said implant comprises argon.  
     
     
         5 . The isolation structure of    claim 1    wherein said implant comprises oxygen.  
     
     
         6 . The isolation structure of    claim 1    wherein said implant comprises germanium.  
     
     
         7 . The isolation structure of    claim 1    wherein said implant comprises nitrogen.  
     
     
         8 . The isolation structure of    claim 1    wherein said implant comprises indium and antimony.  
     
     
         9 . The isolation structure of    claim 8    wherein said indium and antimony implant comprises a nearly electrically neutral combination.  
     
     
         10 . The isolation structure of    claim 1    wherein said implant comprises boron and phosphorus.  
     
     
         11 . The isolation structure of    claim 10    wherein said boron and phosphorus comprises a nearly electrically neutral combination.  
     
     
         12 . A method for reducing the damaging effects of latch-up in CMOS devices comprising the steps of: 
 a) providing a semiconductor substrate;    b) defining a shallow trench in said semiconductor substrate; and    c) implanting a mobility degrading species below said shallow trench.    
     
     
         13 . The method of    claim 12    wherein said mobility degrading species comprises n-type and p-type species in combination to provide low net dopant profile change.  
     
     
         14 . The method of    claim 12    wherein said mobility degrading species comprises a neutral species to provide low dopant profile change.  
     
     
         15 . The method of    claim 12    wherein said mobility degrading species comprises argon.  
     
     
         16 . The method of    claim 12    wherein said mobility degrading species comprises oxygen.  
     
     
         17 . The method of    claim 12    wherein said mobility degrading species comprises germanium.  
     
     
         18 . The method of    claim 12    wherein said mobility degrading species comprises nitrogen.  
     
     
         19 . The method of    claim 12    wherein said mobility degrading species comprises indium and antimony.  
     
     
         20 . The method of    claim 12    wherein said mobility degrading species comprises boron and phosphorus.