Floating gate method and device

Abstract

The present invention provides a novel integrated circuit device, which has a flash memory cell. The flash memory cell ( 100 ) has a tunnel dielectric layer ( 113 ) overlying a surface of a semiconductor substrate. A floating gate layer ( 107 ) is defined overlying the tunnel dielectric layer. The gate layer has an edge defined thereon, where a sidewall spacer ( 108 ) extends along and on the edge. The sidewall spacer includes a first portion defined adjacent to the edge and a second portion extending from the first portion to a region substantially outside the edge. The combination of the sidewall spacer and the gate layer provide a novel surface for increasing gate coupling ratio.

What is claimed is:  
     
         1 . A method for forming an integrated circuit device, said integrated circuit comprising a flash memory cell, said method comprising: 
 forming a tunnel dielectric layer overlying a surface of a semiconductor substrate;    forming a floating gate layer overlying the tunnel dielectric layer, the gate layer having an edge defined thereon; and    forming a sidewall spacer extending along and on the edge and extending beyond the edge, the sidewall spacer comprising a first portion defined adjacent to the edge and a second portion extending from the first portion to a region substantially outside the edge.    
     
     
         2 . The method of    claim 1    wherein the integrated circuit device is a flash EEPROM device.  
     
     
         3 . The method of    claim 1    wherein the floating gate layer comprises polysilicon.  
     
     
         4 . The method of    claim 1    wherein the tunnel dielectric layer comprises oxide.  
     
     
         5 . The method of    claim 1    wherein the sidewall spacer comprises polysilicon.  
     
     
         6 . The method of    claim 1    wherein the sidewall spacer is made of substantially the same material as the floating gate layer.  
     
     
         7 . The method of    claim 1    wherein the steps of forming the floating gate layer and the sidewall spacer comprises: 
 forming a first polysilicon layer overlying the tunnel dielectric layer;  
 forming an oxide layer overlying the first polysilicon layer;  
 patterning the first polysilicon layer and the oxide layer to define the floating gate layer having the edge, said floating gate layer having a patterned layer of oxide thereon;  
 forming a second polysilicon layer overlying the floating gate layer, the edge, and the patterned oxide;  
 removing horizontal portions of the second polysilicon layer while leaving vertical portions of the polysilicon layer intact to define the sidewall spacer on the edge and an edge portion of the patterned oxide; and  
 selectively removing the patterned oxide leaving the first portion of the sidewall spacer defined adjacent to the edge and the second portion extending from the first portion to the region substantially outside the edge.  
 
     
     
         8 . The method of    claim 1    wherein the sidewall is in electrical contact with the floating gate layer.  
     
     
         9 . The method of    claim 1    further comprising a step of forming a control gate layer overlying the floating gate layer and the sidewall.  
     
     
         10 . An integrated circuit device, said integrated circuit comprising a flash memory cell, said flash memory cell comprising: 
 a tunnel dielectric layer overlying a surface of a semiconductor substrate;    a floating gate layer overlying the tunnel dielectric layer, the floating gate layer having an edge defined thereon; and    a sidewall spacer extending along and on the edge and extending beyond the edge, the sidewall spacer comprising a first portion defined adjacent to the edge and a second portion extending from the first portion to a region substantially outside the edge.    
     
     
         11 . The device of    claim 10    wherein the integrated circuit device is a flash EEPROM device.  
     
     
         12 . The device of    claim 10    wherein the floating gate layer comprises polysilicon.  
     
     
         13 . The device of    claim 10    wherein the tunnel dielectric layer comprises oxide.  
     
     
         14 . The device of    claim 10    wherein the sidewall spacer comprises polysilicon.  
     
     
         15 . The device of    claim 10    wherein the sidewall spacer is substantially the same material as the floating gate layer.  
     
     
         16 . The device of    claim 10    wherein the sidewall is in electrical contact with the floating gate layer.  
     
     
         17 . The device of    claim 10    further comprising a control gate layer overlying the floating gate layer and the sidewall.