Fabrication method to approach the conducting structure of a dram cell with straight forward bit line

Abstract

A method for fabricating a conducting structure for a semiconductor device is described. A first dielectric layer is formed on a substrate. The first dielectric layer is etched by using a first photoresist layer, to form original contact holes for exposing surface of the substrate. The first dielectric layer is etched by using a second photoresist layer which is aligned with desired contact holes selected from the original contact holes, to broaden top region of part of the desired contact holes as offset landing regions. A conductive layer is deposited in the desired contact holes, which includes the offset landing region, original contact holes, and on the first dielectric layer. Surface of the conductive layer is planarized to expose the first dielectric layer. In this planarization, original contact structures and desired contact structures having landing plugs are formed, which landing plugs are defined by the first and second photoresist layer. A second dielectric layer is deposited on the first dielectric layer, the original contact structures, and the desired contact structures;. Bit line contacts are formed in the second dielectric layer, wherein the bit line contacts are aligned and contacted with offset sites of the landing plugs. Bit lines are formed on the bit line contacts, to provide the bit lines in a substantially straight shape.

What is claimed is:  
     
         1 . A method for fabricating a conducting structure for a semiconductor device, which comprises following steps: 
 forming a first dielectric layer on a substrate;    etching the first dielectric layer by using a first photoresist layer, thereby forming original contact holes for exposing surface of the substrate;    etching the first dielectric layer by using a second photoresist layer which is aligned with desired contact holes selected from the original contact holes, thereby broadening top region of part of the desired contact holes as offset landing regions;    depositing a conductive layer in the desired contact holes, which includes the offset landing region, original contact holes, and on the first dielectric layer;    planarizing surface of the conductive layer for exposing the first dielectric layer, thereby forming original contact structures and desired contact structures having landing plugs, which are defined by the first and second photoresist layer;    depositing a second dielectric layer on the first dielectric layer, the original contact structures, and the desired contact structures;    forming bit line contacts in the second dielectric layer, the bit line contacts are aligned and contacted with offset sites of the landing plugs; and    forming bit lines on the bit line contacts, thereby providing the bit lines in a substantially straight shape.    
     
     
         2 . The method of    claim 1   , said step of forming the contact hole and said step of forming the offset landing region are exchangeable.  
     
     
         3 . The method of    claim 1   , wherein said offset landing pad and said desired contact structures are formed by one photoresist layer.  
     
     
         4 . The method of    claim 1   , wherein said step of planarizing comprising an etching process.  
     
     
         5 . The method of    claim 1   , wherein said step of planarizing comprising a CMP process.