Apparatus and method for an improved master-slave flip-flop with non-overlapping clocks

Abstract

An improved master-slave flip-flop that is characterized by a novel clock generator. The improved flip-flop preserves the true master-slave relationship by ensuring a two step latching process is executed by non-overlapping clocks. The clock generator features an inverter in combination with a current limiter. The current limiter has the effect of shifting the trip point of the inverter such that non-overlapping clocks may be derived from a single master clock signal or a master clock signal and its complement.

What is claimed is:  
     
         1 . An improved flip-flop comprising: 
 a master gating transistor pair;    a master latch coupled to the master gating transistor pair;    a slave gating transistor pair coupled to the master latch;    a slave latch coupled to the slave gating transistor pair;    a clock generator coupled to the master gating transistor pair;    a second clock generator coupled to the master gating transistor pair;    a third clock generator coupled to the slave gating transistor pair; and    a fourth clock generator coupled to the slave gating transistor pair.    
     
     
         2 . The flip-flop in accordance with    claim 1    wherein the first clock generator is comprised of: 
 a current limiter, and  
 an inverter coupled to the current limiter.  
 
     
     
         3 . The flip-flop in accordance with    claim 1    wherein the second clock generator is comprised of: 
 a current limiter, and  
 an inverter coupled to the current limiter.  
 
     
     
         4 . The flip-flop in accordance with    claim 1    wherein the third clock generator is comprised of: 
 a current limiter, and  
 an inverter coupled to the current limiter.  
 
     
     
         5 . The flip-flop in accordance with    claim 1    wherein the fourth clock generator is comprised of: 
 a current limiter, and  
 an inverter coupled to the current limiter.  
 
     
     
         6 . The flip-flop in accordance with claims  2 ,  3 ,  4 , or  5  wherein the current limiter is a current mirror.  
     
     
         7 . The flip-flop in accordance with    claim 1    wherein the first, second, third and fourth clock generators have a common input.  
     
     
         8 . The flip-flop in accordance with    claim 1    wherein the first and third clock generators have a common input.  
     
     
         9 . The flip-flop in accordance with    claim 8    wherein the second and fourth clock generators have a common input.  
     
     
         10 . The flip-flop in accordance with    claim 9    wherein the common input to the second and fourth clock generators is the complement of the common input to the first and third clock generators.  
     
     
         11 . The flip-flop in accordance with    claim 1    wherein an output of the first clock generator is the complement of an output of the second clock generator.  
     
     
         12 . The flip-flop in accordance with    claim 1    wherein an output of the third clock generator is the complement of an output of the fourth clock generator.  
     
     
         13 . The flip-flop in accordance with    claim 1    wherein an output of the first clock generator and an output selected from the group consisting of the third clock generator and the fourth clock generator are non-overlapping outputs.  
     
     
         14 . The flip-flop in accordance with    claim 1    wherein an output of the second clock generator and an output selected from the group consisting of the third clock generator and the fourth clock generator are non-overlapping outputs.  
     
     
         15 . The flip-flop in accordance with    claim 1    wherein the first clock generator is directly connected to the second clock generator.  
     
     
         16 . The flip-flop in accordance with    claim 1    wherein the third clock generator is directly connected to the fourth clock generator.  
     
     
         17 . A clock generator for use in an improved flip-flop comprising: 
 a current limiter, and    an inverter coupled to the current limiter.    
     
     
         18 . The clock generator in accordance with    claim 17    wherein the current limiter is a current mirror.  
     
     
         19 . The clock generator in accordance with    claim 17    wherein the inverter is comprised of: 
 a P-channel transistor, and  
 an N-channel transistor coupled to the P-channel transistor.  
 
     
     
         20 . The clock generator in accordance with    claim 19    wherein the current limiter is directly connected to the P-channel transistor.  
     
     
         21 . The clock generator in accordance with    claim 19    wherein the current limiter is directly connected to the N-channel transistor.  
     
     
         22 . The clock generator in accordance with    claim 20    wherein the current limiter causes the trip point of the inverter to approximate the supply voltage minus the threshold voltage of the P-channel transistor.  
     
     
         23 . The clock generator in accordance with    claim 21    wherein the current limiter causes the trip point of the inverter to approximate the threshold voltage of the N-channel transistor.  
     
     
         24 . A clock generator comprising: 
 an N-channel transistor; and    a P-channel transistor coupled to the N-channel transistor,    wherein a trip point of the clock generator is adjusted by a length/width ratio of the N-channel transistor.    
     
     
         25 . A clock generator comprising: 
 an N-channel transistor; and    a P-channel transistor coupled to the N-channel transistor,    wherein a trip point of the clock generator is adjusted by a length/width ratio of the P-channel transistor.    
     
     
         26 . A clock generator comprising: 
 an N-channel transistor; and    a P-channel transistor coupled to the N-channel transistor,    wherein a trip point of the clock generator is adjusted by a gain ratio of the N-channel transistor.    
     
     
         27 . A clock generator comprising: 
 an N-channel transistor; and    a P-channel transistor coupled to the N-channel transistor,    wherein a trip point of the clock generator is adjusted by a gain ratio of the P-channel transistor.    
     
     
         28 . A method of generating non-overlapping clocks for a master-slave flip-flop comprising the steps of: 
 providing a master gating transistor pair;    providing a master latch coupled to the master gating transistor pair;    providing a slave gating transistor pair couple to the master latch;    providing a slave latch coupled to the slave gating transistor pair;    providing a clock generator coupled to the master gating transistor pair;    providing a second clock generator coupled to the master gating transistor pair;    providing a third clock generator coupled to the slave gating transistor pair; and    providing a fourth clock generator coupled to the slave gating transistor pair.    
     
     
         29 . The method in accordance with    claim 28    wherein the step of providing the first clock generator further comprises the steps of: 
 providing a current limiter; and  
 providing an inverter coupled to the current limiter.  
 
     
     
         30 . The method in accordance with    claim 28    wherein the step of providing the second clock generator further comprises the steps of: 
 providing a current limiter; and  
 providing an inverter coupled to the current limiter.  
 
     
     
         31 . The method in accordance with    claim 28    wherein the step of providing the third clock generator further comprises the steps of: 
 providing a current limiter; and  
 providing an inverter coupled to the current limiter.  
 
     
     
         32 . The method in accordance with    claim 28    wherein the step of providing the fourth clock generator further comprises the steps of: 
 providing a current limiter; and  
 providing an inverter coupled to the current limiter.  
 
     
     
         33 . The method in accordance with    claim 28    further comprising the step of providing a common master clock input to the first clock generator, the second clock generator, the third clock generator and the fourth clock generator.  
     
     
         34 . The method in accordance with    claim 28    further comprising the steps of: 
 providing a master clock input to the first clock generator and a complement of the master clock input to the second clock generator; and  
 providing the master clock input to the third clock generator and the complement of the master clock input to the fourth clock generator.  
 
     
     
         35 . A method for generating non-overlapping clocks comprising the steps of: 
 providing a current limiter; and    providing an inverter coupled to the current limiter.    
     
     
         36 . The method for generating non-overlapping clocks in accordance with    claim 35    wherein the step of providing an inverter further comprises the steps of: 
 providing a P-channel transistor; and  
 providing an N-channel transistor coupled to the P-channel transistor.  
 
     
     
         37 . The method in accordance with    claim 36    wherein the step of providing the current limiter is directly connected to the P-channel transistor of the inverter.  
     
     
         38 . The method in accordance with    claim 36    wherein the step of providing the current limiter is directly connected to the N-channel transistor of the inverter.  
     
     
         39 . The method in accordance with    claim 37    wherein the step of directly connecting the current limiter to the P-channel transistor causes the trip point of the inverter to approximate the supply voltage minus the threshold voltage of the P-channel transistor.  
     
     
         40 . The method in accordance with    claim 38    wherein the step of directly connecting the current limiter to the N-channel transistor causes the trip point of the inverter to approximate the threshold voltage of the N-channel transistor.