Semiconductor structure having reduced silicide resistance between closely spaced gates and method of fabrication

Abstract

A semiconductor structure comprising a plurality of gates located on a semiconductor substrate; wherein insulating spacer is provided on sidewalls of the gates; and metallic silicide located between the gates is provided along with a method for its fabrication. A partially disposable spacer permits increased area for silicide formation without degrading the device short channel behavior.

What is claimed is:  
     
         1 . A semiconductor structure comprising a semiconductor substrate; a plurality of gates located on the semiconductor substrate and separated from the semiconductor substrate by a first insulating layer; and wherein a sidewall of at least one gate of the plurality of gates is separated from an adjacent sidewall of an adjacent gate by a distance of about 0.5 μm or less; insulating spacer on sidewalls of the gates; metallic silicide located between the gates on the semiconductor substrate; source/drain doping beneath the metallic silicide; and doped junction between the source/drain doping and the gate channel region and extending beneath the insulating spacer.  
     
     
         2 . The semiconductor structure of    claim 1    wherein the semiconductor substrate is silicon.  
     
     
         3 . The semiconductor structure of    claim 1    wherein the spacer comprises silicon nitride.  
     
     
         4 . The semiconductor structure of    claim 1    wherein the plurality of gates are polycrystalline silicon.  
     
     
         5 . The semiconductor structure of    claim 1    wherein the source/drain doping is located beneath the metallic silicide to a depth of at least about 0.1 μm in the semiconductor.  
     
     
         6 . The semiconductor structure of    claim 1    which further comprises further insulating spacer located between the insulating spacer and sidewall of the gate.  
     
     
         7 . The semiconductor structure of    claim 1    wherein the metallic silicide is titanium silicide.  
     
     
         8 . The semiconductor structure of    claim 1    wherein the metallic silicide is cobalt silicide.  
     
     
         9 . The semiconductor structure of    claim 1    wherein the thickness of the insulating spacer is about 100 to about 500 Å.  
     
     
         10 . The semiconductor structure of    claim 1    wherein the thickness of the insulating spacer is about 300 to about 400 Å.  
     
     
         11 . A method for fabricating a semiconductor structure which comprises providing a semiconductor substrate; providing a plurality of gates located on the semiconductor substrate and separated from the semiconductor substrate by a first insulating layer; providing insulating spacers on sidewalls of the gates; wherein the insulating spacers are generally L-shaped having a vertical portion and a horizontal portion and wherein spacing exists between adjacent L-shaped insulating spacers; implanting source/drain dopant between adjacent L-shaped insulating spacers and beneath the horizontal portion of the L-shaped insulating spacers; removing the horizontal portion of the L-shaped insulating spacers by etching; and forming a metallic silicide in the spacing between remaining vertical portions of the insulating spacers.  
     
     
         12 . The method of    claim 11    wherein the semiconductor substrate is silicon.  
     
     
         13 . The method of    claim 11    wherein the L-shaped insulating layer comprises silicon nitride.  
     
     
         14 . The method of    claim 11    wherein the plurality of gates are polycrystalline silicon.  
     
     
         15 . The method of    claim 11    wherein the spacing between a sidewall of at least one gate and the sidewall of an adjacent gate is about 0.5 μm or less.  
     
     
         16 . The method of    claim 11    which further comprises providing a second insulating spacer between the L-shaped insulating spacer and sidewall of the gate.  
     
     
         17 . The method of    claim 16    which comprises forming the second insulating spacer by chemical vapor deposition of silicon nitride or silicon oxide or both.  
     
     
         18 . The method of    claim 11    wherein the metallic silicide is titanium silicide.  
     
     
         19 . The method of    claim 11    wherein the metallic silicide is cobalt silicide.  
     
     
         20 . The method of    claim 11    wherein the horizontal portion of the L-shaped insulating spacer is removed by reactive ion etching.  
     
     
         21 . The method of    claim 11    which further includes thermally annealing to activate source/drain dopants.  
     
     
         22 . The method of    claim 21    wherein the thermally annealing is carried out after removing the horizontal portion of the L-shaped insulating spacers and before forming the metallic silicide.  
     
     
         23 . The method of    claim 21    wherein the thermally annealing is carried out prior to removing the horizontal portion of the L-shaped insulating spacers.  
     
     
         24 . The method of    claim 21    wherein the annealing is carried out at temperatures of about 950 to about 1050° C.  
     
     
         25 . The method of    claim 11    which further comprises implanting dopants into the substrate between adjacent gates prior to providing the L-shaped spacers.  
     
     
         26 . The method of    claim 25    wherein the dosage of the dopants is about 1E12 to about 1E15.  
     
     
         27 . The method of    claim 11    which comprises forming the L-shaped spacers by depositing a layer of silicon nitride followed by depositing a layer of silicon oxide using TEOS and then directionally etching back the layer of silicon oxide and layer of silicon nitride and then removing the remaining layer of silicon oxide.  
     
     
         28 . The method of    claim 11    wherein the horizontal portion of the L-shaped spacer partially blocks the source/drain implants.  
     
     
         29 . The method of    claim 11    wherein the dosage of the source/drain implants is 1E15 to 5E15.  
     
     
         30 . The method of    claim 11    wherein the thickness of the L-shaped insulating spacers is about 100 to about 500 Å.  
     
     
         31 . The method of    claim 11    wherein the thickness of the L-shaped insulating spacers is about 300 to about 400 Å.