Flash memory device and fabrication method thereof

Abstract

A flash memory device and fabrication method simplify the fabrication process of a semiconductor EEPROM device through a self-aligning process. The device includes a semiconductor substrate in which source and drain regions are defined, a first insulation layer formed on the semiconductor substrate, a first conductive layer pattern formed on a portion of the first insulation layer, sidewall spacers formed of a second conductive layer neighboring each sidewall of the first conductive layer pattern and covered by second and third insulation layers, and a third conductive layer pattern formed on the insulation layers and connected with the first conductive layer pattern.

What is claimed is:  
     
         1 . A memory device, comprising: 
 a substrate;    a first region and a second region in the substrate;    a first insulation layer formed on the substrate;    a first conductive layer formed on a portion of the first insulation layer;    first and second conductive sidewall spacers positioned adjacent to first and second sidewalls of the first conductive layer, respectively;    a second insulation layer formed on the first and second conductive sidewall spacers; and    a second conductive layer formed on the insulation layer, the second conductive layer conductively coupled to the first conductive layer.    
     
     
         2 . The device of    claim 1   , wherein the first and second regions are source and drain regions, respectively, the source and drain regions each include a low density doping region and a high density doping region.  
     
     
         3 . The device of    claim 1   , wherein portions of the first insulation layer are formed over the first and second regions.  
     
     
         4 . The device of    claim 3   , wherein the portions of the first insulation layer formed over the first and second regions are thinner than the portion of the first insulation layer on which the first conductive layer is formed.  
     
     
         5 . The device of    claim 1   , wherein the second insulation layer comprises portions that extend between the sidewall spacers and the first conductive layer.  
     
     
         6 . The device of    claim 1   , wherein the second insulation layer comprises portions formed between the sidewall spacers and the third conductive layer.  
     
     
         7 . The device of    claim 1   , wherein portions of the second insulation layer project above an upper surface of the first conductive layer pattern.  
     
     
         8 . The device of    claim 1   , wherein the first and third conductive layers form control gates.  
     
     
         9 . The device of    claim 1   , wherein the first and second conductive sidewall spacers form a floating gate.  
     
     
         10 . The device of    claim 1   , wherein the first and third conductive layers and the first and second conductive layer sidewall spacers are polysilicon.  
     
     
         11 . A method of making a memory device, comprising the steps of: 
 forming a first insulation layer on a substrate;    forming a first conductive layer pattern on a portion of the first insulation layer;    forming impurity regions in the substrate;    forming a second insulation layer on sidewalls of the first conductive layer pattern;    forming, on each of two sides of the first conductive layer pattern, a conductive sidewall spacer on the second insulation layer and the first insulation layer;    forming a third insulation layer that covers the conductive sidewall spacers; and    forming a third conductive layer pattern on the first, second and third insulation layers, the third conductive layer pattern conductively coupled to the first conductive layer pattern.    
     
     
         12 . The method of    claim 11   , wherein the third insulation layer is formed so that it contacts the first and second insulation layers.  
     
     
         13 . The method of    claim 11   , wherein the step of forming impurity regions in the substrate comprises the steps of: 
 forming low density impurity regions in the substrate; and    forming high density impurity regions in the substrate.    
     
     
         14 . The method of    claim 13   , wherein the step of forming low density impurity regions comprises: 
 forming a nitride film pattern on the first conductive layer pattern;    ion-implanting impurities in the substrate while using the nitride film patterns as a mask; and    removing the nitride film pattern.    
     
     
         15 . The method of    claim 13   , wherein the step of forming high density impurity regions comprises: 
 forming a nitride film pattern on the first conductive layer pattern;    ion-implanting impurities in the substrate while using the nitride film pattern and the conductive sidewall spacers as a mask; and    removing the nitride film pattern.    
     
     
         16 . The method of    claim 11   , wherein the first and third conductive layer patterns form control gates.  
     
     
         17 . The method of    claim 11   , wherein the conductive sidewall spacers form a floating gate.  
     
     
         18 . The method of    claim 11   , wherein the first and third conductive layer patterns and the conductive sidewall spacers are polysilicon.  
     
     
         19 . The method of    claim 11   , wherein the second insulation layer is formed between the conductive sidewall spacers and the first conductive layer pattern.  
     
     
         20 . The method of    claim 11   , wherein the third insulation layer is formed between the conductive layer sidewall spacers and the third conductive layer pattern.  
     
     
         21 . The method of    claim 11   , wherein portions of the second insulation layer and the third insulation layer, which cover the conductive sidewall spacers, project above an upper surface of the first conductive layer pattern.  
     
     
         22 . The method of    claim 13   , wherein a first low density impurity region and a first high density impurity region together form a source region, and wherein a second low density impurity region and a second high density impurity region together form a drain region.  
     
     
         23 . The method of    claim 22   , wherein portions of the first insulation layer are formed over the source and drain regions.  
     
     
         24 . The method of    claim 23   , wherein the portions of the first insulation layer formed over the source and drain regions are thinner than the portion of the first insulation layer on which the first conductive layer is formed.