Bulk single crystal gallium nitride and method of making same
Abstract
A single crystal M*N article, which may be made by a process including the steps of: providing a substrate of material having a crystalline surface which is epitaxially compatible with M*N; depositing a layer of single crystal M*N over the surface of the substrate; and removing the substrate from the layer of single crystal M*N, e.g., with an etching agent which is applied to the substrate to remove same, to yield the layer of single crystal M*N as said single crystal M*N article. The bulk single crystal M*N article is suitable for use as a substrate for the fabrication of microelectronic structures thereon, to produce microelectronic devices comprising bulk single crystal M*N substrates, or precursor structures thereof.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A method of making a single crystal M*N article, including the steps of:
providing a substrate of material having a crystalline surface which is epitaxially compatible with M*N, depositing a layer of single crystal M*N over a surface of the substrate; and removing the substrate from the layer of single crystal M*N while the crystal is close to the growth temperature, to recover the layer of single crystal M*N as a single crystal M*N article.
2 . A method according to claim 1 , wherein the substrate of crystalline material is formed of a material selected from the group consisting of silicon, silicon carbide, and gallium arsenide, and the substrate is etchably removed from the layer of single crystal M*N at or near the growth temperature, by etching of the substrate using a gas which etches the substrate material but does not etch the single crystal M*N material.
3 . A method according to claim 1 , wherein the layer of single crystal M*N is deposited directly on said surface of the substrate.
4 . A method according to claim 1 , wherein an intermediate layer of epitaxially related crystalline material is formed directly on said surface of the substrate, and the layer of single crystal M*N is deposited directly on an upper surface of the intermediate layer.
5 . A method according to claim 4 , wherein the intermediate layer of epitaxially related crystalline material comprises a protective layer deposited thereon prior to growth of the M*N layer, so that the protective layer will prevent decomposition of the single crystal substrate while M*N growth is proceeding.
6 . A method according to claim 4 , wherein the intermediate layer of epitaxially related crystalline material is formed either in situ or ex situ.
7 . A method according to claim 4 , wherein the intermediate layer of epitaxially related crystalline material includes an etch stop layer.
8 . A method according to claim 1 , wherein the substrate material comprises a material selected from the group consisting of silicon, silicon carbide, gallium arsenide and sapphire, MgAl 2 O 4 , MgO, ScAlMgO 4 , LiAlO 2 , LiGaO 2 , ZnO, graphite, glass, M*N, SiO 2 , twist-bonded substrate structures, silicon-on-insulator (SOI) substrates, compliant substrates, and substrates containing buried implant species.
9 . A method according to claim 4 , wherein the intermediate layer of epitaxially related crystalline material comprises a strained layer superlattice comprising from 5 to 100 alternating monolayers of two materials selected from the group consisting of AlN, InN, GaN and alloys of SiC with one or more of AlN, InN, and GaN.
10 . A method according to claim 1 , wherein the substrate has a similar thermal coefficient of expansion to the M*N layer.
11 . A method according to claim 1 , wherein the substrate crystalline material or a component of the substrate crystalline material is diffused out of the substrate into the M*N layer, for incorporation of the substrate crystalline material or a component thereof in the M*N layer as a dopant thereof.
12 . A method according to claim 11 , wherein the substrate crystalline material comprises silicon and wherein the silicon substrate is etchably removed with HCl gas to yield the M*N layer having a silicon-doped M*N surface region for formation of ohmic contacts thereon.
13 . A method according to claim 1 , wherein the layer of single crystal M*N comprises a GaN layer.
14 . A method according to claim 1 , wherein the layer of single crystal M*N comprises an MGaN layer, wherein M is a metal compatible with Ga and N in the composition MGaN, and the composition MGaN is stable at standard temperature and pressure (25° C. and 1 atmosphere pressure) conditions.
15 . A method according to claim 14 , wherein M is selected from the group consisting of Al and In.
16 . A method according to claim 1 , where M*N is selected from the group consisting of GaN, SiC and alloys of SiC with one or more of AlN, GaN and InN.
17 . A method according to claim 1 , wherein hydrogen is implanted in the substrate, so that during the deposition of M*N on the substrate, the hydrogen causes in situ fracture of the substrate to separate the substrate from the layer of M*N.
18 . A method according to claim 1 , where the single crystal M*N layer comprises a compositionally graded ternary metal nitride selected from the group consisting of AlGaN, InGaN, and AlInN.
19 . A method according to claim 1 , where the single crystal M*N layer is doped.
20 . A method according to claim 19 , wherein the single crystal M*N layer is doped with a dopant selected from the group consisting of Si, Ge, S, Se, Mg, Zn, Be, V, and Fe.
21 . Bulk single crystal M*N.
22 . Bulk single crystal GaN.
23 . Bulk single crystal MGaN, wherein M is a metal compatible with Ga and N in the composition MGaN, and the composition MGaN is stable at standard temperature and pressure (25° C. and 1 atmosphere pressure) conditions.
24 . Bulk single crystal MGaN according to claim 23 , wherein M is selected from the group consisting of Al and In.
25 . Bulk single crystal MM′GaN, wherein M and M′ are metals compatible with Ga and N in the composition MM′GaN, and the composition MM′GaN is stable at standard temperature and pressure (25° C. and 1 atmosphere pressure) conditions.
26 . A bulk single crystal M*N article of cylindrical or disc-shaped form wherein the diameter is at least 200 micrometers and the thickness is at least 1 micrometer.
27 . A bulk single crystal M*N article of cylindrical or disc-shaped form, having a thickness of at least 100 micrometers and the diameter is at least 2.5 centimeters.
28 . A bulk single crystal M*N article according to claim 21 , wherein the bulk single crystal M*N comprises a surface having a microelectronic device structure or substructure formed thereon.
29 . A bulk single crystal M*N article according to claim 21 , comprising a doped surface region.
30 . A bulk single crystal M*N article according to claim 29 , wherein the doped surface region comprises silicon-doped M*N.
31 . A bulk single crystal M*N article according to claim 30 , wherein the silicon-doped surface region has an ohmic contact structure fabricated thereon.
32 . A bulk single crystal M*N article according to claim 21 , where the single crystal M*N comprises a compositionally graded ternary metal nitride selected from the group consisting of AlGaN, InGaN, and AlInN.
33 . A bulk single crystal M*N article according to claim 21 , wherein the single crystal M*N is doped with a dopant selected from the group consisting of Si, Ge, S, Se, Mg, Zn, Be, V, and Fe.
34 . A bulk single crystal M*N article according to claim 21 , wherein the single crystal M*N is n-doped.
35 . A bulk single crystal M*N article according to claim 21 , wherein the single crystal M*N is p-doped.
36 . A bulk single crystal M*N article according to claim 21 , wherein the single crystal M*N is semi-insulatively-doped.
37 . A microelectronic structural assembly, comprising a bulk single crystal GaN substrate having fabricated thereon a microelectronic device or a device precursor structure thereof.
38 . A microelectronic structural assembly according to claim 37 , comprising a microelectronic device selected from the group consisting of LEDs, lasers, detectors, and transistors, and device precursor structures thereof.Join the waitlist — get patent alerts
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