US2001008497A1PendingUtilityA1

Semiconductor device

36
Priority: Apr 10, 1998Filed: Jan 16, 2001Published: Jul 19, 2001
Est. expiryApr 10, 2018(expired)· nominal 20-yr term from priority
Inventors:Masashi HoriguchiMasayuki NakamuraSadayuki OhkumaKazuhiko KajigayaYoshinobu Nakagome
G11C 11/4076G11C 8/12G11C 2211/4067G11C 11/406G11C 5/147G11C 11/40615G11C 2211/4068G11C 11/40618G11C 2207/2227G11C 11/4091G11C 7/1072G11C 5/14G11C 5/063G11C 11/4074G11C 11/4087
36
PatentIndex Score
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Claims

Abstract

A semiconductor device comprising a plurality of memory banks and a plurality of power supply circuits corresponding to the memory banks. Each of the memory banks is independently activated by an activating command. Given an externally supplied voltage, each of the power supply circuits outputs a predetermined internal supply voltage. Each power supply circuit has its output connected to the corresponding memory bank. In response to a command for activating one of the memory banks, the corresponding power supply circuit is activated while the remaining power supply circuits is deactivated.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
         1 . A semiconductor device comprising: 
 a first power supply circuit which receives an externally supplied voltage and outputs an internal supply voltage; and    a second power supply circuit which receives said externally supplied voltage and outputs said internal supply voltage,    wherein said first power supply circuit is not in operation when said semiconductor device is in a power down mode, and    wherein said second power supply circuit is continuously in operation.    
     
     
         2 . A semiconductor device according to    claim 1   , 
 wherein said externally supplied voltage is larger than said internal supply voltage, and    wherein each of said first and second power supply circuits is a voltage limiter.    
     
     
         3 . A semiconductor device according to    claim 1   , further comprising a plurality of memory cells, 
 wherein said semiconductor device is a semiconductor memory device.    
     
     
         4 . A semiconductor device comprising: 
 a plurality of memory cells; and    a voltage generating circuit which receives a first voltage and outputs a second voltage,    wherein said voltage generating circuit is not in operation while said semiconductor device is in a power down mode and is in operation while said semiconductor device is in an auto refresh mode.    
     
     
         5 . A semiconductor device according to    claim 4   , 
 wherein said first voltage is supplied from outside of said semiconductor device,    wherein said first voltage is larger than said second voltage, and    wherein said voltage generating circuit is a voltage limiter circuit.    
     
     
         6 . A semiconductor device comprising: 
 a voltage generating circuit which receives a first voltage and generates a second voltage,    wherein said voltage generating circuit is not in operation while said semiconductor device is in a low power dissipation mode and is in operation while said semiconductor device is in a refresh mode.    
     
     
         7 . A semiconductor device according to    claim 6   , 
 wherein said refresh mode is an auto refresh mode.    
     
     
         8 . A semiconductor device according to    claim 6   , 
 wherein said first voltage is supplied from outside of said semiconductor device,    wherein said first voltage is larger than said second voltage, and    wherein said voltage generating circuit is a voltage limiter circuit.    
     
     
         9 . A semiconductor device comprising: 
 a voltage generation circuit which receives a first voltage and outputs a second voltage,    wherein said voltage generation circuit is not in operation while said semiconductor device is in a first mode which is set by a first command and is in operation while said semiconductor device is in a second mode which is set by a second command, and    wherein said first mode is a power down mode.    
     
     
         10 . A semiconductor device according to    claim 9   , 
 wherein said second mode is an auto refresh mode.    
     
     
         11 . A semiconductor device according to    claim 9   , 
 wherein said first voltage is supplied from outside of said semiconductor device,    wherein said first voltage is larger than said second voltage, and    wherein said voltage generation circuit is a voltage limiter.    
     
     
         12 . A semiconductor device comprising: 
 a plurality of memory cells;    a first voltage generation circuit which receives a first voltage and outputs a second voltage; and    a second voltage generation circuit which receives said first voltage and outputs said second voltage,    wherein said first voltage generation circuit is inoperative when said semiconductor device is in a power down mode and is operative when said semiconductor device is in an auto refresh mode, and    wherein said second voltage generation circuit is operative when said semiconductor device is in said power down mode and in said auto refresh mode.    
     
     
         13 . A semiconductor device according to    claim 12   , 
 wherein said first voltage is supplied from outside of said semiconductor device,    wherein said first voltage is larger than said second voltage, and    wherein each of said first and second voltage generation circuit is a voltage limiter.    
     
     
         14 . A semiconductor device comprising: 
 a plurality of memory cells;    a first voltage generation circuit which receives a first voltage and outputs a second voltage; and    a second voltage generation circuit which receives said first voltage and outputs said second voltage,    wherein said first voltage generation circuit is inoperative while said semiconductor device is in a power down mode and is operative when said semiconductor device is in a refresh mode, and    wherein said second voltage generation circuit is operative when said semiconductor device is in said power down mode and said refresh mode.    
     
     
         15 . A semiconductor device according to    claim 14   , 
 wherein said second mode is an auto refresh mode.    
     
     
         16 . A semiconductor device according to    claim 14   , wherein said second mode is a self refresh mode.  
     
     
         17 . A semiconductor device according to    claim 14   , wherein said first voltage is supplied from outside of said semiconductor device, 
 wherein said first voltage is larger than said second voltage, and    wherein each of said first and second voltage generation circuits is a voltage limiter.    
     
     
         18 . A semiconductor device comprising: 
 a plurality of memory cells;    a first voltage generation circuit which receives a first voltage and outputs a second voltage; and    a second voltage generation circuit which receives said first voltage and outputs said second voltage, wherein said first voltage generation circuit is intermittently in operation when said semiconductor device is in a first refresh mode and is continuously in operation when said semiconductor device is in a second refresh mode, and    wherein said second voltage generation circuit is continuously in operation when said semiconductor device is in said first refresh mode and is continuously in operation when said semiconductor device is in said second refresh mode.    
     
     
         19 . A semiconductor device according to    claim 18   , wherein said first refresh mode is a self refresh mode and second said mode is in auto refresh mode.  
     
     
         20 . A semiconductor device according to    claim 18   , wherein said first voltage is supplied from outside of said semiconductor device, 
 wherein said first voltage is larger than said second voltage, and    wherein each of said first and second voltage generation circuits is a voltage limiter.    
     
     
         21 . A semiconductor device comprising: 
 a plurality of memory cells;    a first circuit receiving a first voltage and generating a second voltage;    a second circuit receiving said first voltage and generating said second voltage; and    a third circuit receiving said first voltage and generating said second voltage,    wherein said first circuit is inoperative when said semiconductor device is in a power down mode and is operative when said semiconductor device is in a refresh mode,    wherein said second circuit is operative when said semiconductor device is in said power down mode and is in said refresh mode, and    wherein said third circuit is operative in response to an active command for said plurality of memory cells.    
     
     
         22 . A semiconductor device according to    claim 21   , wherein said refresh mode is an auto refresh mode.  
     
     
         23 . A semiconductor device according to    claim 21   , wherein said refresh mode is a self refresh mode.  
     
     
         24 . A semiconductor device according to    claim 21   , wherein said first voltage is supplied from outside of said semiconductor device, 
 wherein said first voltage is larger than said second voltage, and    wherein each of said first, second and third circuits is a voltage limiter.

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