Semiconductor memory

Abstract

A semiconductor memory includes a plurality of memory cell arrays each composed of a plurality of memory cells, each of the memory cell arrays including a plurality of main word lines, each of which is composed of a pair of sub-word lines each connected to a plurality of memory cells, means for driving the main word lines, power supply voltage supply line driving means connected to the sub-line lines. When a redundant word line used in place of a specific sub-word line including a defective sense amplifier is activated, the number of the sub-word lines activated when a data input/output is conducted is different from the number of sub-word lines activated in a refreshing operation. When the data input/output is conducted, a replacement of a sub-word line is executed on the basis of the result of a comparison between an externally supplied row address and an internally stored row address. When the refreshing operation is conducted, the replacement of the sub-word line is executed on the basis of an output of an internal refresh address counter and simultaneously with an ordinary refreshing operation.

1 . A semiconductor memory including a plurality of memory cell arrays each composed of a plurality of memory cells, each of said memory cell arrays including a plurality of main word lines, each of which is composed of a pair of sub-word lines each connected to a plurality of memory cells, means for driving said main word lines, power supply voltage supply line driving means connected to said sub-line lines, in which when a redundant word line used in place of a specific sub-word line including a defective sense amplifier is activated, the number of said sub-word lines activated when a data input/output is conducted is different from the number of sub-word lines activated in a refreshing operation, and wherein when the data input/output is conducted, a replacement of a sub-word line is executed on the basis of the result of a comparison between an externally supplied row address and an internally stored row address, and when the refreshing operation is conducted, the replacement of said sub-word line is executed on the basis of an output of an internal refresh address counter and simultaneously with an ordinary refreshing operation.  
     
     
         2 . A semiconductor memory claimed in    claim 1    wherein the semiconductor memory is a synchronous dynamic random access memory.  
     
     
         3 . A semiconductor memory claimed in    claim 2    wherein the refreshing operation is executed on the basis of only an internal address.  
     
     
         4 . A semiconductor memory claimed in    claim 1    further including a replacement address comparing means provided for each of said memory cell arrays, to generate a replacement discrimination signal on the basis of an internal active command generated when data is inputted/outputted, a refresh command signal and an internal row address signal.  
     
     
         5 . A semiconductor memory claimed in    claim 4    wherein said replacement address comparing means includes a defective address storing means for storing a defective address concerning the sub-word line, and a comparing means for comparing said stored defective address with said internal row address signal.  
     
     
         6 . A semiconductor memory claimed in    claim 5    wherein said replacement address comparing means is so configured to output a refresh operation stopping signal for stopping the refresh operation for a sub-word line including a defective sense amplifier when the sub-word line including the defective sense amplifier is selected.  
     
     
         7 . A semiconductor memory claimed in    claim 4    wherein said replacement address comparing means does not execute the comparison of the replacement row address in the refresh operation.  
     
     
         8 . A semiconductor memory claimed in    claim 4    wherein said replacement address comparing means includes a comparing means for comparing said internal row address with a predetermined replacement address concerning the redundant sub-word line performing the replacement operation in the refresh operation.  
     
     
         9 . A method for driving a semiconductor memory including a plurality of memory cell arrays each composed of a plurality of memory cells, each of said memory cell arrays including a plurality of main word lines, each of which is composed of a pair of sub-word lines each connected to a plurality of memory cells, means for driving said main word lines, power supply voltage supply line driving means connected to said sub-line lines, the method including driving the semiconductor memory in such a manner that when a redundant word line used in place of a specific sub-word line including a defective sense amplifier is activated, the number of said sub-word lines activated when a data input/output is conducted is different from the number of sub-word lines activated in a refreshing operation, executing a replacement of a sub-word line on the basis of the result of a comparison between an externally supplied row address and an internally stored row address, when the data input/output is conducted, and executing the replacement of said sub-word line on the basis of an output of an internal refresh address counter and simultaneously with an ordinary refreshing operation, when the refreshing operation is conducted.  
     
     
         10 . A method claimed in    claim 9    wherein the semiconductor memory is a synchronous dynamic random access memory.  
     
     
         11 . A method claimed in    claim 10    wherein the refreshing operation is executed on the basis of only an internal address.  
     
     
         12 . A method claimed in    claim 9    wherein by a replacement address comparing means provided for each of said memory cell arrays, a replacement discrimination signal is generated on the basis of an internal active command generated when data is inputted/outputted, a refresh command signal and an internal row address signal.  
     
     
         13 . A method claimed in    claim 12    wherein said replacement address comparing means includes a defective address storing means for storing a defective address concerning the sub-word line, and a comparing means for comparing said stored defective address with said internal row address signal.  
     
     
         14 . A method claimed in    claim 13    wherein said replacement address comparing means is so configured to output a refresh operation stopping signal for stopping the refresh operation for a sub-word line including a defective sense amplifier when the sub-word line including the defective sense amplifier is selected.  
     
     
         15 . A method claimed in    claim 12    wherein said replacement address comparing means does not execute the comparison of the replacement row address in the refresh operation.  
     
     
         16 . A method claimed in    claim 12    wherein said replacement address comparing means includes a comparing means for comparing said internal row address with a predetermined replacement address concerning the redundant sub-word line performing the replacement operation in the refresh operation.  
     
     
         17 . A semiconductor memory comprising a plurality of main word lines selected and activated by a first external row address signal or a first internal row address signal generated internally in the semiconductor memory, a plurality of power supply voltage supplying lines selected and activated by a second external row address signal or a second internal row address signal generated internally in the semiconductor memory, a plurality of sub-word lines connected to a gate electrode of a plurality of memory cells and selected and activated by the main word line and the power supply voltage supplying lines, means for activating the sub-word lines for being ready to read or write a memory cell data in response to a first command, and means for activating the sub-word lines for being ready to rewrite a memory cell data in response to a second command, the number of the sub-word lines included in the sub-word lines connected to the power supply voltage supplying line and activated by the first external row address signal being different from the number of the sub-word lines activated by the second external row address signal.  
     
     
         18 . A semiconductor memory claimed in    claim 17    further including a redundant main word line and redundant sub-word lines connected to the redundant main word line.  
     
     
         19 . A semiconductor memory claimed in    claim 17    further including a means for storing the row address of the defective memory cell and a first discriminating means for comparing the row address of the defective memory cell with the internal row address to generate a first discrimination signal.  
     
     
         20 . A semiconductor memory claimed in    claim 19    further including a means for activating the redundant main word line on the basis of said first discrimination signal.  
     
     
         21 . A semiconductor memory claimed in    claim 19    further including a means for selecting and activating said power supply voltage supplying line on the basis of said first discrimination signal.  
     
     
         22 . A semiconductor memory claimed in    claim 17    further including a second discriminating means for comparing a respective inherent row address with the internal row address so as to generate a second discrimination signal.  
     
     
         23 . A semiconductor memory claimed in    claim 22    further including a means for activating the redundant main word line on the basis of said second discrimination signal.  
     
     
         24 . A semiconductor memory claimed in    claim 17    wherein, when said first command is inputted, the main word line or the redundant main word line is selected and activated on the basis of the internal row address signal and the first discrimination signal, and also, the power supply voltage supply line is selected and activated on the basis of the internal row address signal and the first discrimination signal, and when said second command is inputted, the main word line and the power supply voltage supply line are selected and activated on the basis of the internal row address signal, and the redundant main word line is selected and activated on the basis of the second discrimination signal.  
     
     
         25 . A semiconductor memory claimed in    claim 24    further including a means for inactivating the main word line on the basis of the internal row address signal and the first discrimination signal, when the second command indicative of the refresh operation is inputted.