Co-planar si and ge composite substrate and method of producing same

Abstract

A semiconductor structure including a silicon wafer having silicon regions, and at least one Ge x Si 1−x region integrated within the silicon regions. The silicon and Ge x Si 1−x regions can be substantially coplanar surfaces. The structure can include at least one electronic device configured in the silicon regions, and at least one electronic device of III-V materials configured in said at least one Ge x Si 1−x region. The structure can be, for example, an integrated HI-V/Si semiconductor microchip. In accordance with another embodiment of the invention there is provided a method of fabricating a semiconductor structure, including providing a silicon wafer with a surface; forming a pattern of vias within the surface of the wafer; and depositing regions of Ge x Si 1−x within vias. The method can include the step of processing the wafer so that the wafer and Ge x Si 1−x regions have substantially coplanar surfaces. Another embodiment provides a method of fabricating a semiconductor structure, including providing a silicon wafer with a surface; depositing regions of Ge x Si 1−x to the surface of the silicon wafer; and depositing silicon to the surface such that the deposited Ge x Si 1−x regions are integrated within silicon.

What is claimed is:  
     
         1 . A semiconductor structure comprising: 
 a silicon wafer having silicon regions; and    at least one Ge x Si 1−x  region integrated within said silicon regions.    
     
     
         2 . The semiconductor structure of    claim 1   , wherein said silicon and Ge x Si 1−x  regions comprise substantially coplanar surfaces.  
     
     
         3 . The semiconductor structure of    claim 1    further comprising at least one electronic device configured in said silicon regions.  
     
     
         4 . The semiconductor structure of    claim 1    further comprising at least one electronic device of III-V materials configured in said at least one Ge x ,Si 1−x  region.  
     
     
         5 . The semiconductor structure of    claim 1    further comprising at least one electronic device of III-V materials configured in said at least one Ge x Si 1−x  region.  
     
     
         6 . An integrated III-V/Si semiconductor microchip, comprising: 
 a silicon wafer having silicon regions;    at least one electronic device configured in said silicon regions;    at least one Ge x Si 1−x  region integrated within said silicon regions; and    at least one electronic device of III-V materials configured in said at least one Ge x ,Si 1−x  region.    
     
     
         7 . An integrated GeSi/Si semiconductor microchip, comprising: 
 a silicon wafer having silicon regions;    at least one electronic device configured in said silicon regions;    at least one Ge x Si 1−x  region integrated within said silicon regions; and    at least one electronic device of GeSi material configured in said at least one Ge x Si 1−x  region.    
     
     
         8 . A method of fabricating a semiconductor structure, comprising: 
 providing a silicon wafer with a surface;    forming a pattern of vias within the surface of said wafer; and    depositing regions of Ge x Si 1−x  within said vias.    
     
     
         9 . The method of    claim 8    further comprising processing said wafer so that said wafer and Ge x Si 1−x  regions have substantially coplanar surfaces.  
     
     
         10 . A method of fabricating a semiconductor structure, comprising: 
 providing a silicon wafer with a surface;    depositing regions of Ge x Si 1−x  to said surface of said silicon wafer; and    depositing silicon to said surface such that said deposited Ge x Si 1−x  regions are integrated within silicon.