Extending the data word length for data transmission and data processing cross-reference to related application

Abstract

The invention relates to a method for expanding a first, N-digit data word in two's complement representation to produce a second, (N+M)-digit data word for data transmission and data processing, and to an apparatus for carrying out the method. To provide a method which imposes no increased hardware requirements on an apparatus for carrying out the method and which prevents numerical-range overflows when the converted number is negated, the invention proposes putting the digits of the original number into the more significant places of the target binary number, retaining the order of digits, and entering the digit “1” at least once into the first M-places of the second binary number.

1 . Data word expansion method for expanding a first, N-digit data word in two's complement representation to produce a second, (N+M)-digit data word, where N and M are natural numbers greater than 0 comprising the steps of 
 putting the digits in the Nth to 1st place ( 4 ,  3 ) of the first data word into the (N+M)th to (M+1)th place of the second data word, retaining the order of digits, and at least one of the first M places of the second data word is set to the logic value “1”.    
     
     
         2 . Method according to    claim 1   , further comprising the step of setting precisely one of the first M places of the second data word to the logic value “1”.  
     
     
         3 . Method according to    claim 2   , further comprising the step of putting the logic value “0” into the Mth place of the second data word.  
     
     
         4 . Method according to    claim 3   , further comprising putting the logic value “1” into the least significant place of the second data word, and the logic value “0” into each of the subsequent places up to and including the Mth place.  
     
     
         5 . Apparatus for extending a data word length from N to (N+M) digits, comprising 
 a first circuit device for outputting an N-digit data word in two's complement representation, the N-digit output of which is connected to the more significant places of an (N+M)-bit-wide data channel, retaining the order of places, and    a second circuit device designed for outputting a prescribed M-digit data word having at least one logic “1”, the M-digit output of which is connected to the less significant M places of the (N+M)-bit-wide data channel.    
     
     
         6 . The apparatus of    claim 5    further comprising a third circuit device, whose (N+M)-wide input is connected to the (N+M)-wide data channel.