US2001002716A1PendingUtilityA1

SOI device and method of isolation thereof

Priority: Jun 30, 1998Filed: Dec 18, 2000Published: Jun 7, 2001
Est. expiryJun 30, 2018(expired)· nominal 20-yr term from priority
Inventors:Won Chang Lee
H10W 10/17H10W 10/014H10W 10/13H10W 10/012H10W 10/181H10W 10/061H10P 90/1906H10D 86/01H10D 86/201H10P 50/282
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Claims

Abstract

The present invention provides an SOI device and its isolation method capable of solving both Well-resistance and punch-through problems. To realize foregoing device, there is provided a semiconductor layer that a region in which a field oxide film having relatively wider width is formed later, is thicker than a region in which a field oxide film having relatively narrower width is formed later. Those field oxide films having different widths with an equal thickness are formed on the field regions of the semiconductor layer. Herein, the thickness of the semiconductor layer below the field oxide film having relatively wider width is thicker than the thickness of the semiconductor layer below the field oxide film having relatively narrower width owing to the fact that the semiconductor layer has various thicknesses according to the respective regions. Accordingly, the Well-resistance at the field oxide film region having relatively wider width is reduced and the punch-through problem at the field oxide film region having relatively narrower width is prevented.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
         1 . An SOI device comprising: 
 an SOI substrate having a stack structure of a base layer, a buried oxide layer disposed on the base layer, and a semiconductor layer disposed on the buried oxide layer;    first field oxide films having a first width and second field oxide films having a second width which is narrower than the first width, both formed on the semiconductor layer at a depth spaced with the buried oxide layer; and    a transistor formed at an active region of the semiconductor layer defined by the first and second field oxide films,    wherein a region that the first field oxide film is formed, is thicker than other regions in the semiconductor layer, and a distance between the first field oxide films and the buried oxide layer is larger than a distance between the second field oxide film and the buried oxide layer.    
     
     
         2 . The SOI device of    claim 1   , further comprising a diffusion area for well-pick up formed at the semiconductor layer.  
     
     
         3 . The SOI device of    claim 2   , wherein the diffusion area for well-pick up has the same conductivity type with the semiconductor layer of the lower portion of a gate electrode.  
     
     
         4 . A method of isolating SOI device comprising the steps of: 
 providing an SOI substrate having a stack structure of a base layer, a buried oxide layer disposed on the base layer, and a semiconductor layer on the buried oxide layer, wherein the semiconductor layer has first field oxide regions having a first width and second field oxide regions having a second width which is narrower than the first width;    removing a selected thickness of the semiconductor layer excluding the first field region;    forming an isolation mask by masking active regions between those field regions which are adjacent each other on the semiconductor layer and by exposing the first and second field regions;    forming first field oxide films having a first width and second field oxide films having a second width which is narrower than the first width by oxidizing the exposed first and second field regions; and    removing the isolation mask.    
     
     
         5 . The method of    claim 4   , wherein the isolation mask is made of a nitride layer.  
     
     
         6 . The method of    claim 5   , wherein the step of forming the isolation mask comprises the steps of: 
 depositing a nitride layer on the semiconductor layer of the SOI substrate;    forming a photoresist pattern for masking the active region of the semiconductor layer on the nitride layer;    removing the exposed nitride layer region by a dry etching process using the photoresist pattern; and    removing the photoresist pattern.    
     
     
         7 . The method of    claim 4   , wherein the isolation mask exposes larger region than the first field region.  
     
     
         8 . A method of isolating SOI device comprising the steps of: 
 providing an SOI substrate having a stack structure of a base layer, a buried oxide layer disposed on the base layer, and a semiconductor layer on the buried oxide layer, wherein the semiconductor layer has first field oxide regions having a first width and second field oxide regions having a second width which is narrower than the first width;    removing a selected thickness of the semiconductor layer region excluding the first field region;    forming an isolation mask by masking active regions between those field regions which are adjacent each other on the semiconductor layer and by exposing the first and second field regions;    forming a first trench having a first width and a second trench having a second width which is narrower than the first width by removing equally the first and second field regions of the exposed semiconductor layer as much as a selected thickness according to a dry etching process using the isolation mask, wherein both trenches are spaced with the buried oxide layer;    forming first and second field oxide films by filling the first and second trenches with an insulating layer; and    removing the isolation mask.    
     
     
         9 . The method of    claim 8   , wherein the isolation mask is made of a nitride layer.  
     
     
         10 . The method of    claim 9   , wherein the step of forming the first and second field oxide films comprises the steps of: 
 depositing an insulating layer with a thickness sufficient to fill the first and second trenches on the overall surface of a resultant; and    etching the insulating layer until the isolation mask is exposed.    
     
     
         11 . The method of    claim 10   , wherein the step of etching the insulating layer is performed according to an etch-back or a chemical mechanical polishing(CMP) process.  
     
     
         12 . The method of    claim 8   , wherein the isolation mask exposes larger region than the first field region.

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