Method of fabricating a dual -damascene structure in an integrated cirtcuit with multilevel-interconnect strcture

Abstract

A semiconductor fabrication method is provided for the fabrication of a dual-damascene structure in an integrated circuit with a multilevel-interconnect structure. This method is characterized in that, after the dual-damascene hole is formed, a conformal barrier/adhesive layer is first formed over all the sidewalls of the dual-damascene hole, but not filling the dual-damascene hole. An anisotropic etching process is then performed to etch away the part of the conformal barrier/adhesive layer that is laid at the bottom of the dual-damascene hole and subsequently the underlying part of the topping layer until exposing the metallization layer. Finally, a conductive material, such as copper, is deposited into the remaining void portion of the dual-damascene hole. The deposited conductive material and the remaining part of the conformal barrier/adhesive layer in the dual-damascene hole in combination constitute the intended dual-damascene structure. The conformal barrier/adhesive layer serves as a diffusion protective layer for the dielectric layers, which can subsequently help prevent diffusion of the spluttering metal atoms from the metallization layer during the RIE (Reaction Ion Etching) process into the dielectric layers.

What is claimed is:  
     
         1 . A method for fabricating a damascene structure in an integrated circuit constructed on a semiconductor substrate which is already formed with a metallization layer at a predefined location in the substrate and a topping layer formed over the substrate and covering the metallization layer, the method comprising the steps of: 
 forming a dielectric layer over the topping layer;    forming a damascene hole in the dielectric layer, which exposes the topping layer;    forming a conformal barrier/adhesive layer to a predefined thickness over all the sidewalls of the damascene hole, the exposed part of the topping layer, and the surface of the dielectric layer, but not filling the damascene hole;    performing an etching process to etch away the bottom part of the conformal barrier/adhesive layer that is laid at the bottom of the damascene hole directly over the topping layer and subsequently the underlying part of the topping layer until exposing the metallization layer; and    depositing a conductive material into the remaining void portion of the damascene hole, wherein the deposited conductive material and the remaining part of the conformal barrier/adhesive layer in combination constitute the intended damascene structure.    
     
     
         2 . The method of    claim 1   , wherein the conformal barrier/adhesive layer is formed from a material selected from the group consisting of tantalum, tantalum nitride, titanium, and titanium nitride.  
     
     
         3 . The method of    claim 1   , wherein the conductive material is copper.  
     
     
         4 . The method of    claim 1   , wherein the etching process is an anisotropic etching process.  
     
     
         5 . The method of    claim 4   , wherein the anisotropic etching process is an RIE process.  
     
     
         6 . The method of    claim 1   , further comprising the step of forming a topping layer over the second dielectric layer.  
     
     
         7 . A method for fabricating a dual-damascene structure in an integrated circuit constructed on a semiconductor substrate which is already formed with a metallization layer at a predefined location in the substrate and a topping layer formed over the substrate and covering the metallization layer, the method comprising the steps of: 
 forming a dielectric layer over the topping layer;    forming a dual-damascene hole in the dielectric layer, which exposes the topping layer;    forming a conformal barrier/adhesive layer to a predefined thickness over all the sidewalls of the dual-damascene hole, the exposed part of the topping layer, and the surface of the dielectric layer, but not filling the dual-damascene hole;    performing an etching process to etch away the bottom part of the conformal barrier/adhesive layer that is laid at the bottom of the dual-damascene hole directly over the topping layer and subsequently the underlying part of the topping layer until exposing the metallization layer; and    depositing a conductive material into the remaining void portion of the dual-damascene hole, wherein the deposited conductive material and the remaining part of the conformal barrier/adhesive layer in combination constitute the intended dual-damascene structure.    
     
     
         8 . The method of    claim 7   , wherein the conformal barrier/adhesive layer is formed from a conformal barrier/adhesive material selected from the group consisting of tantalum, tantalum nitride, titanium, and titanium nitride.  
     
     
         9 . The method of    claim 7   , wherein the conductive material is copper.  
     
     
         10 . The method of    claim 7   , wherein the etching process is an anisotropic etching process.  
     
     
         11 . The method of    claim 10   , wherein the anisotropic etching process is an RIE process.  
     
     
         12 . The method of    claim 7   , further comprising the step of: 
 forming a topping layer over the second dielectric layer.    
     
     
         13 . A method for fabricating a dual-damascene structure in an integrated circuit constructed on a semiconductor substrate which is already formed with a metallization layer at a predefined location in the substrate and a first topping layer formed over the substrate and covering the metallization layer, the method comprising the steps of: 
 forming a first dielectric layer over the first topping layer;    forming an etch-end layer over the first dielectric layer;    forming an opening at a predefined location in the etch-end layer directly above the metallization layer;    forming a first dielectric layer over the etch-end layer;    etching away a selected part of the second dielectric layer until reaching the etch-end layer to thereby form a metallization-layer trench in the first dielectric layer directly above the metallization layer;    etching away the part of the first dielectric layer that is not masked by the etch-end layer until exposing the first topping layer to thereby form a via hole in the first dielectric layer, wherein the via hole in the first dielectric layer and the metallization-layer trench in the second dielectric layer in combination constitute a dual-damascene hole;    forming a conformal barrier/adhesive layer to a predefined thickness over all the sidewalls of the dual-damascene hole and also over the surface of the second dielectric layer, but not filling the dual-damascene hole;    etching away the bottom part of the conformal barrier/adhesive layer that is laid at the bottom of the dual-damascene hole directly over the first topping layer and subsequently the underlying part of the first topping layer until exposing the metallization layer;    depositing a conductive material into the remaining void portion of the dual-damascene hole and over the conformal barrier/adhesive layer to a predefined thickness;    performing a surface removal process to remove those portions of the conductive layer and the conformal barrier/adhesive layer that are laid above the surface of the second dielectric layer, wherein the remaining part of the conductive layer and the remaining part of the conformal barrier/adhesive layer in combination constitute the intended dual-damascene structure; and    forming a second topping layer over the second dielectric layer to cover the dual-damascene structure.    
     
     
         14 . The method of    claim 13   , wherein the conductive layer is formed from copper.  
     
     
         15 . The method of    claim 13   , wherein the conductive layer is formed through a CVD process.  
     
     
         16 . The method of    claim 13   , wherein the first topping layer is formed from silicon nitride.  
     
     
         17 . The method of    claim 13   , wherein the conformal barrier/adhesive layer is formed from a conformal barrier/adhesive material selected from the group consisting of tantalum, tantalum nitride, titanium, and titanium nitride.  
     
     
         18 . The method of    claim 13   , wherein the etching of the bottom part of the conformal barrier/adhesive layer and the underlying part of the first topping layer is carried out through an anisotropic etching process.  
     
     
         19 . The method of    claim 18   , wherein the anisotropic etching process is an RIE process.