Semiconductor device

Abstract

A semiconductor device comprising a plurality of memory banks and a plurality of power supply circuits corresponding to the memory banks. Each of the memory banks is independently activated by an activating command. Given an externally supplied voltage, each of the power supply circuits outputs a predetermined internal supply voltage. Each power supply circuit has its output connected to the corresponding memory bank. In response to a command for activating one of the memory banks, the corresponding power supply circuit is activated while the remaining power supply circuits is deactivated.

What is claimed is:  
     
         1 . A semiconductor device comprising: 
 a semiconductor substrate having a surface;    a power supply circuit which receives an externally supplied voltage and outputs an internal supply voltage;    a memory array portion in said surface, in which a plurality of memory cells are arranged;    an internal circuit portion having MOSFETS;    bit lines each extending in a column direction, each of said bit lines being connected to predetermined ones of said memory cells;    first voltage supply lines, each extending in said column direction and formed over said bit lines and said word lines; and    second voltage supply lines, each extending in said row direction and formed over said bit lines and said word lines, said second voltage supply lines being formed by a conductive layer which is different from that of said first voltage supply lines,    wherein said first and second voltage supply lines are connected to each other at the intersection of said first and second voltage supply lines,    wherein one of said first and second voltage supply lines receives said internal supply voltage, and    wherein said internal supply voltage is supplied to said MOSFETs in said internal circuit portion from said power supply circuit via said first and second voltage supply lines.    
     
     
         2 . A semiconductor device according to    claim 1   , wherein said first voltage supply lines are comprised of a first conductive layer and said second voltage supply lines are comprised of a second conductive layer, and wherein said first conductive layer is over said second conductive layer.  
     
     
         3 . A semiconductor device comprising: 
 a semiconductor substrate;    a voltage generating circuit which receives a first voltage and outputs a second voltage;    a plurality of memory cells formed on said semiconductor substrate;    a plurality of bit lines each extending in a column direction, each of said plurality of bits lines being connected to said memory cells;    a plurality of word lines each extending in a row direction, each of said plurality of word lines being connected to predetermined ones of said memory cells;    a plurality of sense amplifiers coupled to said plurality of bit lines;    a plurality of first lines each extending in said column direction and formed over said bit lines and said word lines, said plurality of first lines being formed in a first layer; and    a plurality of second lines each extending in said row direction and formed over said bit lines and said word lines, said plurality of first and second lines,    wherein said plurality of first and second lines are connected to each other at intersections of said plurality of first and second lines,    wherein one of said plurality of first and second lines is coupled to receive said second voltage, and    wherein said second voltage is supplied to said plurality of sense amplifiers from said voltage generating circuit via said plurality of first and second lines.    
     
     
         4 . A semiconductor device according to    claim 3   , further comprising a second voltage generating circuit which receives said first voltage and outputs said second voltage to one of said plurality of first and second lines.  
     
     
         5 . A semiconductor device according to    claim 3   , wherein said first voltage is supplied from outside of said semiconductor device, 
 wherein said first voltage is larger than said second voltage, and    wherein said voltage generating circuit is a voltage limiter circuit.    
     
     
         6 . A semiconductor device according to    claim 3   , 
 wherein each of said plurality of memory cells is comprised of a MOSFET and a capacitor element connected in series.    
     
     
         7 . A semiconductor device according to    claim 3   , 
 wherein said plurality of first and second lines are comprised of a metal.    
     
     
         8 . A semiconductor device comprising; 
 a semiconductor substrate;    a voltage generation circuit which receives a first voltage and generates a second voltage,    a plurality of memory cells formed on said semiconductor substrate;    a plurality of bit lines;    a plurality of word lines;    an amplifier coupled to said plurality of bit lines;    a plurality of first lines each extending in a first direction and formed over said bit lines and said word lines, said plurality of first lines formed in a first layer; and    a plurality of second lines each extending in a second direction and formed over said bit lines and said word lines, said plurality of second lines being formed in a second layer which is different from said first layer, said second direction being different from said first direction,    wherein said plurality of first and second lines are connected to each other at least at one of intersections of said first and second lines,    wherein one of said plurality of first and second lines receives said second voltage, and    wherein said second voltage is supplied to said amplifier from said voltage generation circuit via said plurality of first and second lines.    
     
     
         9 . A semiconductor device according to    claim 8   , 
 wherein said first voltage is supplied from outside of said semiconductor device,    wherein said first voltage is larger than said second voltage, and    wherein said voltage generation circuit is a voltage limiter circuit.    
     
     
         10 . A semiconductor device according to    claim 8   , 
 wherein each of said plurality of memory cells is comprised of a MOSFET and a capacitor element connected in series.    
     
     
         11 . A semiconductor device according to    claim 8   , wherein said plurality of first and second lines are comprised of a metal.  
     
     
         12 . A semiconductor device comprising: 
 a semiconductor substrate;    a voltage generating circuit which receives a first voltage and generates a second voltage;    a plurality of memory cells formed on said semiconductor substrate;    a plurality of first voltage lines each extending in a first direction and formed over said plurality of memory cells, said plurality of first voltage lines being formed in a first layer; and    a plurality a second lines each extending in a second direction and formed over said plurality of memory cells, said plurality of second lines being formed in a second layer which is different from said first layer, aid second direction being different from said first direction;    wherein aid plurality of first and second lines are connected to each other at least at one of intersections of said first and second voltage lines, and    wherein one of said plurality of first and second lines receives said second voltage.    
     
     
         13 . A semiconductor device according to    claim 12   , further comprising a second voltage generating circuit which receives said first voltage and outputs said second voltage to one of said plurality of first and second voltage lines.  
     
     
         14 . A semiconductor device according to    claim 12   , 
 wherein said first voltage is supplied from outside of said semiconductor device;    wherein said first voltage is larger than said second voltage; and    wherein said voltage generating circuit is a voltage limiter circuit.    
     
     
         15 . A semiconductor device according to    claim 12   , 
 wherein each of said plurality of memory cells is comprised of a MOSFET and a capacitor element connected in series.    
     
     
         16 . A semiconductor device according to    claim 12   , 
 wherein said plurality of first and second lines are comprised of a metal.    
     
     
         17 . A semiconductor device according to    claim 12   , further comprising a sense amplifier coupled to one of said plurality of bit lines, 
 wherein said second voltage is supplied to said sense amplifier from said voltage generating circuit via said plurality of first and second voltage lines.    
     
     
         18 . A semiconductor device according to    claim 12   , further comprising a plurality of sense amplifiers from said voltage generating circuit via said plurality of first and second voltage lines.  
     
     
         19 . A semiconductor device according to    claim 12   , 
 wherein at least one of said plurality of memory cells are formed under the intersection of said first and second voltage lines.