Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device capable of restraining a leakage current at a n-p junction of source/drain regions and a manufacturing method of the semiconductor device. A trench is formed in the source/drain regions, a main surface of the source/drain regions is removed at a time of forming the trench and a surface area of the source/drain regions is increased as compared with that before forming the trench. In this manner, a stress per unit area concentrated on the source/drain regions in the vicinity of ends of an isolating oxide film is reduced, and any occurrence of minute defects is restrained. As a result, leakage current caused by any minute defects due to the stress is reduced, and a refresh pause time is prolonged, and in other words, characteristics of a refresh operation can be improved.

Claims:  
     
         1 . A semiconductor device comprising: 
 a semiconductor substrate;    an isolating insulation film formed on an isolated region of a main surface of said semiconductor substrate;    a pair of source/drain regions formed in an active region surrounded by the isolated region of the main surface of said semiconductor substrate;    a trench formed in said source/drain regions;    a gate electrode formed on a main surface of the active region of said semiconductor substrate through a gate insulating film;    at least one interlayer insulating film formed to coat said isolating insulation film, said source/drain regions, said trench, and said gate electrode;    a wiring layer reaching said trench through an opening provided on said at least one interlayer insulating film; and    a capacitor connected to one of said pair of source/drain regions through said wiring layer.    
     
     
         2 . A semiconductor device as defined in    claim 1   , wherein said trench is formed deeper into said semiconductor substrate than said source/drain regions, and said wiring layer comprises a first wiring layer formed by filling up said trench with a material having an energy band gap larger than silicon, and a second wiring layer connected to said first wiring layer.  
     
     
         3 . A semiconductor device as defined in    claim 2   , wherein said first wiring layer is composed of silicon carbide.  
     
     
         4 . A semiconductor device as defined in    claim 1   , wherein said trench is formed deeper into said semiconductor substrate than said source/drain regions, and said semiconductor device further comprises a silicon oxide film formed on a boundary surface between said wiring layer and said semiconductor substrate.  
     
     
         5 . A semiconductor device as defined in    claim 1   , wherein said trench is formed on a surface of said source/drain regions, said one of said pair of source/drain regions connected to said capacitor is adjacent to said isolating insulation film, and said trench formed on the surface of said source/drain regions forms a part of a surface of an end of said isolating insulation film.  
     
     
         6 . A semiconductor device comprising: 
 a semiconductor substrate;    an isolating insulation film formed on an isolated region of a main surface of said semiconductor substrate;    a pair of source/drain regions formed in an active region surrounded by the isolated region of the main surface of said semiconductor substrate;    a gate electrode formed on a main surface of the active region of said semiconductor substrate through a gate insulating film;    at least one an interlayer insulating film formed to coat said isolating insulation film, said source/drain regions, said trench, and said gate electrode;    a wiring layer formed by filling up a contact hole reaching said source/drain regions through an opening provided on said at least one interlayer insulating film;    a capacitor connected to one of said pair of source/drain regions through said wiring layer; and    a film restraining a leakage current formed in said wiring layer apart from said capacitor.    
     
     
         7 . A semiconductor device as defined in    claim 6   , wherein said wiring layer and said film are both composed of polycrystal silicon, and an impurity concentration of said film is lower than an impurity concentration of said wiring layer.  
     
     
         8 . A semiconductor device as defined in    claim 6   , wherein said film is formed of a silicon oxide film.  
     
     
         9 . A semiconductor device as defined in    claim 6   , wherein said film is composed of a material having an energy band gap larger than of said wiring layer.  
     
     
         10 . A semiconductor device as defined in    claim 9   , wherein said film is formed of silicon carbide.  
     
     
         11 . A manufacturing method of a semiconductor device comprising the steps of: 
 forming an isolating insulation film on an isolated region of a main surface of a semiconductor substrate;    forming a gate electrode on the main surface of said semiconductor substrate through a gate insulating film;    forming a pair of source/drain regions in an active region surrounded by said isolated region of the main surface of said semiconductor substrate;    forming a side wall on a side of said gate electrode;    forming a trench by etching said source/drain regions;    forming a first wiring layer by filling up said trench with a first conductive material;    forming at least one interlayer insulating film to coat said isolating insulation film, said source/drain regions, said trench, and said gate electrode;    forming an opening reaching from a surface of said at least one interlayer insulating film to a surface of said first wiring layer;    forming a second wiring layer by filling up said opening with a second conductive material; and    forming a capacitor connected to one of said pair of source/drain regions through said first and second wiring layers.    
     
     
         12 . A manufacturing method of a semiconductor device as defined in    claim 11   , wherein said trench is formed deeper into said semiconductor substrate than said source/drain regions, and the first conductive material is composed of silicon carbide.  
     
     
         13 . A manufacturing method of a semiconductor device as defined in    claim 11   , further comprising the steps of: 
 forming a silicon oxide film by thermal oxidation, after forming said trench deeper into said semiconductor substrate than said source/drain regions; and    leaving said silicon oxide film only on a part of a bottom surface of said trench where said semiconductor substrate is exposed, by etching back.    
     
     
         14 . A manufacturing method of a semiconductor device as defined in    claim 11   , comprising the steps of: 
 forming a mask coating a surface of said isolating insulation film other than at an end of said isolating insulation film; and    removing said one of said pair of source/drain regions to which said capacitor is connected and a surface of said isolating insulation film by etching using the side wall and said mask, and forming a trench shallower into said semiconductor substrate than said source/drain region and in which a part of the surface of the end of said isolating insulation film is removed.    
     
     
         15 . A manufacturing method of a semiconductor device comprising the steps of: 
 forming an isolating insulation film on an isolated region of a main surface of a semiconductor substrate;    forming a gate electrode on the main surface of said semiconductor substrate through a gate insulating film;    forming a pair of source/drain regions in an active region surrounded by said isolated region of the main surface of said semiconductor substrate;    forming a side wall on a side of said gate electrode;    forming at least one interlayer insulating film to coat said isolating insulation film, said source/drain regions, said trench, and said gate electrode;    forming an opening for forming a wiring layer connected electrically to one of said pair of source/drain region on said at least one interlayer insulating film;    forming a first wiring layer of said wiring layer by filling up to about halfway of said opening with a first layer of a first material;    forming a second wiring layer of said wiring layer with a second material placed on the first wiring layer;    forming a third wiring layer of said wiring layer with a second layer of said first material placed on the second wiring layer; and    forming a capacitor connected electrically to said wiring layer including said first, second and third wiring layers.    
     
     
         16 . A manufacturing method of a semiconductor device as defined in    claim 15   , wherein the first and second materials are both composed of a polycrystal silicon, and the second material includes impurities of lower concentration than of the first material.  
     
     
         17 . A manufacturing method of a semiconductor device as defined in    claim 15   , wherein said second material is a highly resistant material.  
     
     
         18 . A manufacturing method of a semiconductor device as defined in    claim 15   , wherein said second material has an energy band gap larger than of said first material.  
     
     
         19 . A manufacturing method of a semiconductor device as defined in    claim 15   , wherein said second material is composed of silicon carbide.