Ferroelectric capacitor and a method for manufacturing thereof

Abstract

It is an object of the present invention to provide a ferroelectric capacitor which maintains high ferroelecticity. A silicon oxide layer 2, a lower electrode 12, a ferroelectric layer 8 and an upper electrode 10 are formed on a silicon substrate 2. The lower electrode 12 is formed by an alloy layer made of iridium and platinum. The alloy layer of the lower electrode 12 can be formed under appropriate lattice constant correspond with a kind and composition of the ferroelectric layer 8. So that, a ferroelectric layer having excellent ferroelectricity can be obtained. Also, it is possible to prevent vacancy of oxygen in the ferroelectric layer 8.

What is claimed is:  
     
         1 . A ferrolectric capacitor comprising: 
 a) a substrate of semiconductor;    b) a lower electrode located on the substrate of semiconductor, having an alloy layer made of platinum and iridium;    c) a ferroectric layer formed on the lower electrode contacting with the alloy layer of the lower electrode;    d) an upper electrode formed on the ferroelectric layer.    
     
     
         2 . A ferroelectric capacitor comprising: 
 a) a substrate of semiconductor;    b) a lower electrode formed on the substrate of semiconductor, having an iridium layer;    c) a ferroelectric layer formed on the lower electrode, contacting with the iridium layer of the lower electrode;    d) an upper electrode formed on the ferroelectric layer.    
     
     
         3 . A ferroelectric capacitor in accordance with    claim 1    or    claim 2   , wherein the lower electrode is located on the silicon oxide layer formed on the substrate of semiconductor, and the lower electrode having a buffer layer contacting with the silicon oxide layer under the alloy layer or the iridium layer.  
     
     
         4 . A method for manufacturing a ferroelectric capacitor, comparing the steps of: 
 a) step for forming a lower electrode on a substrate of semiconductor by an alloy layer made of platinum and iridium, or an iridium layer using sputtering;    b) step for carrying out thermal treatment to the lower electrode in above 700° C.;    c) step for forming a ferroelectric layer contacting on the alloy layer;    d) step for forming an upper electrode on the ferroelectric layer.    
     
     
         5 . A method for manufacturing a ferroelectric capacitor, comparing the steps of: 
 a) step for forming a silicon oxide layer on a substrate of semiconductor;    b) step for forming a buffer layer on the silicon oxide layer;    c) step for forming a lower electrode on a titanium layer by an alloy layer made of platinum and iridium, or an iridium layer;    d) step for carrying out thermal treatment to the lower electrode in above 700° C.;    e) step for forming a ferroelectric layer on the lower electrode;    f) step for forming an upper electrode on the ferroelectric layer.    
     
     
         6 . A method for manufacturing a ferroelectric capacitor in accordance with    claim 4    or    claim 5   , wherein the step for carrying out thermal treatment is also served as thermal treatment for forming the ferroelectric layer.  
     
     
         7 . A ferrolectric capacitor comprising: 
 a) a substrate of semiconductor;    b) a lower electrode located on the substrate of semiconductor;    c) a ferroelectric layer forming on a lower electrode;    d) an upper electrode formed on the ferroelectric layer characterized by that at least either one of the lower electrode or the upper electrode comprises an iridium oxide layer.    
     
     
         8 . A ferroelctric capacitor in accordance with    claim 7   , wherein a silicon oxide layer is located between the substrate of semiconductor and the lower electrode.  
     
     
         9 . A ferroelectric capacitor in accordance with    claim 8   , wherein a buffer layer is located between the silicon oxide layer and the lower electrode.  
     
     
         10 . A ferroelectric capacitor in accordance with    claim 7   ,    claim 8    or    claim 9   , wherein the lower electrode is made of the iridium oxide layer and the iridium layer or the platinum layer formed thereon.  
     
     
         11 . A method for manufacturing a ferroelectric capacitor, comprising steps of: 
 a) step for forming a lower electrode on a substrate of semiconductor;    b) step for forming a ferroelectric layer on the lower electrode;    c) step for forming an upper electrode on the ferroelctric layer;    characterized by that at least either one of the step for forming the lower electrode or the step for forming the upper electrode is contained into a step for forming the iridium oxide layer by sputtering.    
     
     
         12 . A ferroelctric capacitor in accordance with    claim 7   , wherein at least either one of the lower electrode or the upper electrode comprises an iridium oxide layer formed by oxidize the iridium layer and upper part of the iridium layer.  
     
     
         13 . A ferroelectric capacitor in accordance with    claim 12   , wherein a silicon oxide layer is located between the substrate of semiconductor and the lower electrode.  
     
     
         14 . A ferroelectric capacitor in accordance with    claim 13   , wherein a buffer layer is located between the silicon oxide layer and the lower electrode.  
     
     
         15 . A method for manufacturing a ferroelectric capacitor, comprising steps of: 
 a) step for forming a lower electrode on a substrate of semiconductor;    b) step for forming a ferroelctric layer on the lower electrode;    c) step for forming an upper electrode on the ferroelectric layer;    characterized by that at least either one of the step for forming the lower electrode or the step for forming the upper electrode is contained into a step for forming an iridium layer by sputtering and then a step for forming the iridium oxide layer at least on surface of the iridium oxide layer.    
     
     
         16 . A ferroelectric capacitor comprising: 
 a) an under layer made of poly silicon layer, poly silicide layer or tungsten layer;    b) an iridium oxide layer located on the under layer;    c) an iridium layer or a platinum layer located on the iridium oxide layer;    d) a high dielectric constant thin film or a ferroelctric layer located on the iridium layer or the platinum layer;    e) an upper layer located on the high dielectric constant thin film or the ferroelctric layer.    
     
     
         17 . A ferroelctric capacitor in accordance with    claim 16   , wherein the iridium layer is located between the under layer and the iridium oxide layer.  
     
     
         18 . An nonvolatile memory device comprising: 
 a) a silicon substrate formed a source region and a drain region wherein;    b) a silicon oxide layer located on a channel region formed between the source region and the drain region in the silicon substrate;    c) an upper layer formed on the silicon oxide layer, made of a poly silicon layer, a poly silicide layer or a tantalum layer;    d) an iridium oxide layer formed on the under layer;    e) an iridium layer or a platinum layer formed on the iridium oxide layer;    f) a high dielectric constant thin film or a ferrolectric layer formed on the platinum layer or the iridium layer;    g) an upper electrode formed on either the high dielectric constant thin film or the ferrolectric layer.    
     
     
         19 . A ferroelectric capacitor comprising: 
 a) an under layer made of a poly silicon layer, a poly silicide layer or a tungsten layer;    b) a middle layer located on the under layer contained at least an iridium oxide layer;    c) a high dielectric constant thin film or a ferroelectric layer located on the middle layer;    d) an upper electrode located on the high dielectric constant thin film or the ferroelectric layer.