Semiconductor device with no step between well regions

Abstract

In a semiconductor device having a high voltage transistor, a first well region of the high voltage transistor is formed in a semiconductor substrate as a channel region. The first well region has a first conductive type. Second well regions of the high voltage transistor are formed in the semiconductor substrate as a source region and a drain region to sandwich the first well region. The second well region has a second conductive type. A surface of the first region and surfaces of the second well regions have a flat plane.

What is claimed is:  
     
         1 . A semiconductor device having a high voltage transistor, comprising: 
 a first well region of said high voltage transistor formed in a semiconductor substrate as a channel region and having a first conductive type; and    second well regions of said high voltage transistor formed in said semiconductor substrate as a source region and a drain region to sandwich said first well region and having a second conductive type, wherein a surface of said first region and surfaces of said second well regions have a flat plane.    
     
     
         2 . A semiconductor device according to    claim 1   , further including a first transistor operating in a higher voltage than a second transistor and formed on said semiconductor substrate, in addition to said high voltage transistor.  
     
     
         3 . A semiconductor device according to    claim 2   , wherein said first transistor is formed on said semiconductor substrate to have, as a channel region, a third well region of said first conductive type.  
     
     
         4 . A semiconductor device according to    claim 2   , wherein said semiconductor device comprises a memory section including said first transistor and a peripheral section including said high voltage transistor.  
     
     
         5 . A semiconductor device according to    claim 4   , wherein said semiconductor device is a non-volatile semiconductor memory device.  
     
     
         6 . A semiconductor memory device comprising: 
 a memory circuit section formed on a semiconductor substrate; and    a peripheral circuit section formed on said semiconductor substrate, for driving and controlling said memory circuit section, wherein a surface of a region where said memory circuit section is formed is lower in height than that of a region where said peripheral circuit section is formed.    
     
     
         7 . A semiconductor memory device according to    claim 6   , wherein said surface of said region where said peripheral circuit section is formed is flat.  
     
     
         8 . A semiconductor memory device according to    claim 6   , wherein said memory circuit section includes a plurality of non-volatile semiconductor memory cell transistors.  
     
     
         9 . A semiconductor memory device according to    claim 6   , wherein said peripheral circuit section includes a plurality of high voltage transistors.  
     
     
         10 . A semiconductor memory device according to    claim 9   , wherein each of said plurality of high voltage transistors has as a channel region a first well region of a first conductive type, and as source and drain regions second well regions of a second conductive type.  
     
     
         11 . A semiconductor memory device according to    claim 10   , wherein a well region of said semiconductor substrate where said memory circuit section is formed is of said first conductive region.  
     
     
         12 . A semiconductor memory device according to    claim 6   , wherein said surface of said region where said memory circuit is formed is used for a reference mark.  
     
     
         13 . A method of manufacturing a semiconductor device, comprising the steps of: 
 forming a recess region for a memory cell region on a surface of a semiconductor substrate;    performing a first ion implantation of first impurity ions of a first conductive type to said semiconductor substrate to form a well region of said first conductive type,    forming a resist film on said semiconductor substrate;    patterning said resist film;    performing a second ion implantation of second impurity ions of a second conductive type to said semiconductor substrate using said patterned resist film as a mask; and    heating said semiconductor substrate such that first well regions of said first conductive type and second well regions of said second conductive type are formed.    
     
     
         14 . A method according to    claim 13   , further comprising the step of: 
 forming a memory circuit section in said memory cell region and a peripheral circuit section in a region other than said memory cell region.    
     
     
         15 . A method according to    claim 13   , further comprising the step of: 
 forming a reference mark in said recess section.    
     
     
         16 . A method according to    claim 14   , wherein said step of forming a memory circuit section in said memory cell region includes forming non-volatile memory cell transistors of said memory circuit section.  
     
     
         17 . A method according to    claim 14   , wherein said step of forming a peripheral circuit section includes forming high voltage transistors of said peripheral circuit section which drive and control said memory circuit section.  
     
     
         18 . A method according to    claim 13   , wherein said step of performing a second ion implantation includes performing said second ion implantation in a dose amount of said second impurity ions which is more than that of said first impurity ions.  19 . A method according to    claim 13   , wherein said step of performing a second ion implantation includes performing a second ion implantation includes performing said second ion implantation plural times while changing acceleration energy.