Damascene process with anti-reflection coating

Abstract

The present invention proposes a method for improving the damascene process window for metallization and utilizes an anti-reflective coating to increase the precision of the photolithography process. An inter-layer dielectric and an anti-reflective layer are formed in turn on a semiconductor substrate. The inter-layer dielectric is patterned to form the interconnection line regions. A conductive layer is then deposited on the semiconductor substrate and fills the interconnecting line regions. The chemical mechanical polish is performed to remove a portions of the conductive layer exceeding the interconnect line regions and simultaneously remove residual portion of said anti-reflective layer.

What is claimed is:  
     
         1 . A method for improving the damascene process window for metallization, said method comprises: 
 forming a dielectric layer on a semiconductor substrate;    forming an anti-reflective layer on said dielectric layer;    patterning said dielectric layer, thereby forming interconnect line regions in said dielectric layer; and    forming a conductive layer in said interconnect line regions.    
     
     
         2 . The method according to    claim 1   , further comprising following steps to form plugs before said dielectric layer is formed: 
 forming an inter-layer dielectric on said semiconductor substrate;    patterning said inter-layer dielectric to form plug regions in said interlayer dielectric; and    filling said plug regions with conductive materials.    
     
     
         3 . The method according to    claim 2   , further comprising a step for performing a chemical mechanical polishing to planarize said semiconductor substrate after said plug regions is filled.  
     
     
         4 . The method according to    claim 1   , wherein said anti-reflective layer is formed of the material selected from the group consisting of a double film of titanium and titanium nitride (Ti/TiN) and silicon oxynitride (SiON).  
     
     
         5 . The method according to    claim 1   , wherein said interconnect line regions is patterned in said dielectric layer by a photolithography process using I-line as the exposure light source when the anti-reflective layer is formed of double film of titanium and titanium nitride (Ti/TiN).  
     
     
         6 . The method according to    claim 1   , wherein said interconnect line regions is patterned in said dielectric layer by a photolithography process using deep ultra-violet (DUV) as the exposure light source when the anti-reflective layer is formed of silicon oxynitride (SiON).  
     
     
         7 . The method according to    claim 1   , further comprising a step for patterning plug regions in said dielectric layer after said interconnect line regions is formed.  
     
     
         8 . The method according to    claim 2   , further comprising a step for removing a portion of said conductive layer which exceeds said interconnect line regions and simultaneously removing residual portion of said anti-reflective layer.  
     
     
         9 . The method according to    claim 8   , wherein said exceeding portion of said conductive layer and said residual portion of said anti-reflective layer are removed by a chemical mechanical polishing process.  
     
     
         10 . A method for improving the damascene process window for metallization, said method comprises: 
 forming a inter-layer dielectric on said semiconductor substrate;    patterning said inter-layer dielectric to form the plug regions in said inter-layer dielectric; and    filling said plug regions with conductive material    forming an dielectric layer on a semiconductor substrate;    forming an anti-reflective layer on said dielectric layer;    patterning said dielectric layer, thereby forming the interconnect line regions in said dielectric layer;    depositing a conductive layer on said semiconductor substrate, thereby filling said interconnect line regions; and    removing a portions of said conductive layer which exceed said interconnect line regions and simultaneously removing residual portion of said anti-reflective layer.    
     
     
         11 . The method according to    claim 10   , further comprising a step for performing a chemical mechanical polishing to planarize said semiconductor substrate after said plug regions is filled.  
     
     
         12 . The method according to    claim 10   , wherein the anti-reflective layer is formed of the material selected from the group consisting of a double film of titanium and titanium nitride (Ti/TiN) and silicon oxynitride (SiON).  
     
     
         13 . The method according to    claim 10   , wherein said interconnect line regions is patterned in said dielectric layer by a photolithography process using I-line as the exposure light source when the anti-reflective layer is formed of double film of titanium and titanium nitride (Ti/TiN).  
     
     
         14 . The method according to    claim 10   , wherein said interconnect line regions is patterned in said dielectric layer by a photolithography process using deep ultra-violet (DUV) as the exposure light source when the anti-reflective layer is formed of silicon oxynitride (SiON).  
     
     
         15 . The method according to    claim 10   , wherein said exceeding portion of said conductive layer and said residual portion of said anti-reflective layer are removed by a chemical mechanical polishing process.  
     
     
         16 . A method for improving the damascene process window for metallization, said method comprises: 
 forming an inter-layer dielectric on a semiconductor substrate;    forming an anti-reflective layer on said inter-layer dielectric;    patterning said inter-layer dielectric, thereby forming the interconnect line regions in said inter-layer dielectric;    patterning said inter-layer dielectric, thereby forming the plug regions in said inter-layer dielectric    depositing a conductive layer on said semiconductor substrate, thereby filling said interconnect line regions; and    removing a portions of said conductive layer which exceed said interconnect line regions and simultaneously removing residual portion of said anti-reflective layer.    
     
     
         17 . The method according to    claim 16   , wherein the anti-reflective layer is formed of the material selected from the group consisting of a double film of titanium and titanium nitride (Ti/TiN) and silicon oxynitride (SiON).  
     
     
         18 . The method according to    claim 16   , wherein said interconnect line regions is patterned in said inter-layer dielectric by a photolithography process using I-line as the exposure light source when the anti-reflective layer is formed of double film of titanium and titanium nitride (Ti/TiN).  
     
     
         19 . The method according to    claim 16   , wherein said interconnect line regions is patterned in said inter-layer dielectric by a photolithography process using deep ultra-violet (DUV) as the exposure light source when the anti-reflective layer is formed of silicon oxynitride (SiON).  
     
     
         20 . The method according to    claim 16   , wherein said exceeding portion of said conductive layer and said residual portion of said anti-reflective layer are removed by a chemical mechanical polishing process.