Semiconductor device and method of manufacturing the same

Abstract

An embodiment of the present application provides a semiconductor device, including a substrate, a chip, a latch-up protection circuit, and a redistribution layer. The chip is on the substrate. The latch-up protection circuit is separated from the chip in a direction. The redistribution layer transmits a signal between the latch-up protection circuit and the chip.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a substrate;   a first chip disposed on the substrate;   a latch-up protection circuit separated from the first chip in a first direction;   a first redistribution layer configured to transmit a first signal between the latch-up protection circuit and the first chip; and   a second redistribution layer that is disposed under the first chip, electrically coupled to the first chip and separated from the first redistribution layer in the first direction,   wherein the second redistribution layer is configured to input the first signal to the first chip or receive the first signal from the first chip.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the first direction is a horizontal direction, and the first redistribution layer is under the latch-up protection circuit and electrically coupled to the second redistribution layer through the substrate. 
     
     
         3 . The semiconductor device of  claim 1 , further comprising:
 a second chip that is disposed on a surface of the substrate on which the first chip is disposed and electrically coupled to the first redistribution layer through the substrate.   
     
     
         4 . The semiconductor device of  claim 3 , wherein the latch-up protection circuit is disposed in the substrate, and the substrate further comprises:
 a first via configured to electrically couple the second chip to the first redistribution layer; and   a second via configured to electrically couple the first redistribution layer to the second redistribution layer.   
     
     
         5 . The semiconductor device of  claim 1 , further comprising:
 an interposer disposed on the substrate, wherein the latch-up protection circuit is included in the interposer and the first chip is disposed on a surface above the interposer;   a third redistribution layer disposed at a first side of the interposer and electrically coupled to the substrate, wherein the first redistribution layer is disposed at a second side, opposite to the first side, of the interposer; and   a first via that is disposed in the interposer and configured to electrically couple the first redistribution layer to the third redistribution layer.   
     
     
         6 . The semiconductor device of  claim 5 , further comprising:
 a second chip disposed on the surface above the interposer and electrically coupled to the first redistribution layer.   
     
     
         7 . The semiconductor device of  claim 1 , further comprising:
 a via that is disposed between the substrate and the first redistribution layer and configured to receive a second signal from the substrate as the first signal which is transmitted to the latch-up protection circuit through the first redistribution layer,   wherein the latch-up protection circuit comprises:
 a first transistor having a first doped region, a second doped region and a first gate, wherein the first doped region is electrically coupled to the via through a terminal of the first redistribution layer, and the second doped region and the first gate are electrically coupled to a first voltage supply terminal; and 
 a second transistor having a third doped region, a fourth doped region and a second gate, wherein the third doped region is electrically coupled to the via through the terminal of the first redistribution layer, and the fourth doped region and the second gate are electrically coupled to a second voltage supply terminal. 
   
     
     
         8 . A semiconductor device, comprising:
 a substrate;   a first chip disposed on the substrate;   a latch-up protection circuit separated from the first chip;   a first redistribution layer configured to transmit a first signal between the latch-up protection circuit and the first chip; and   a second chip that is disposed on a surface of the substrate on which the first chip is disposed, wherein the second chip is electrically coupled to the first redistribution layer through the substrate.   
     
     
         9 . The semiconductor device of  claim 8 , wherein the substrate comprises:
 a first conductive structure configured to couple the second chip to the latch-up protection circuit.   
     
     
         10 . The semiconductor device of  claim 9 , wherein the substrate further comprises:
 a second conductive structure configured to transmit a signal between the latch-up protection circuit and the first chip.   
     
     
         11 . The semiconductor device of  claim 9 , further comprising:
 an interconnect structure, comprising:
 an interposer surrounding the latch-up protection circuit. 
   
     
     
         12 . The semiconductor device of  claim 11 , wherein the first chip is disposed on the interconnect structure and the interconnect structure is disposed on the substrate, wherein the semiconductor device further comprises:
 a third chip disposed on the interconnect structure and coupled to the substrate through the interconnect structure.   
     
     
         13 . The semiconductor device of  claim 8 , further comprising:
 an interconnect structure configured to transmit a signal between the first chip and the substrate, the latch-up protection circuit being included in the interconnect structure; and   a third chip disposed on a surface of the interconnect structure with the first chip disposed on the surface of the interconnect structure as well, and coupled to the first chip through the interconnect structure, wherein the second chip and the interconnect structure are disposed on the surface of the substrate,   wherein the first chip and the third chip are configured to execute a first processing operation with a first processing speed, and the first chip and the second chip are configured to execute a second processing operation with a second processing speed slower than the first processing speed.   
     
     
         14 . The semiconductor device of  claim 8 , further comprising:
 an interconnect structure disposed in the substrate and configured to transmit a signal to the latch-up protection circuit,   wherein in a top view, the interconnect structure overlaps the first chip and the second chip.