Semiconductor package

Abstract

A semiconductor package includes a lower package, an upper package on the lower package, and an inter-package connector between the lower package and the upper package. The lower package includes a first redistribution structure, a first semiconductor chip mounted on a first mounting region of the first redistribution structure, a second semiconductor chip mounted on a second mounting region of the first redistribution structure, a molding layer on the first redistribution structure and in contact with a side wall of the first semiconductor chip and a side wall of the second semiconductor chip, and a conductive post passing through the molding layer and electrically connected to the first semiconductor chip through a first redistribution pattern of the first redistribution structure. The upper package is on the molding layer, vertically overlaps with the second mounting region of the first redistribution structure, and does not cover the first semiconductor chip.

What is claimed is: 
     
         1 . A semiconductor package comprising:
 a lower package;   an upper package on the lower package; and   an inter-package connector between the lower package and the upper package,   wherein the lower package includes:
 a first redistribution structure including a first redistribution insulating layer and a first redistribution pattern; 
 a first semiconductor chip mounted on a first mounting region of the first redistribution structure; 
 a second semiconductor chip mounted on a second mounting region of the first redistribution structure, the second mounting region of the first redistribution structure being spaced apart from the first mounting region of the first redistribution structure; 
 a molding layer on the first redistribution structure and in contact with a side wall of the first semiconductor chip and a side wall of the second semiconductor chip, the molding layer having a top surface coplanar with a top surface of the first semiconductor chip in a horizontal direction; and 
 a conductive post on the second mounting region of the first redistribution structure, the conductive post passing through the molding layer and being electrically connected to the first semiconductor chip through the first redistribution pattern of the first redistribution structure, 
   wherein the first semiconductor chip includes a logic chip,   wherein the upper package includes a memory chip electrically connected to the first semiconductor chip through the conductive post,   wherein the upper package vertically overlaps the second mounting region of the first redistribution structure and does not vertically overlap the first semiconductor chip, and   wherein no electronic components are disposed on the first mounting region between the top surface of the first semiconductor chip and an outside of the semiconductor package.   
     
     
         2 . The semiconductor package of  claim 1 , wherein the top surface of the first semiconductor chip is exposed to the outside of the semiconductor package. 
     
     
         3 . The semiconductor package of  claim 1 , further comprising:
 first chip connection bumps between the first semiconductor chip and the first redistribution structure; and   second chip connection bumps between the second semiconductor chip and the first redistribution structure.   
     
     
         4 . The semiconductor package of  claim 1 , further comprising:
 a cover insulating layer covering a portion of the molding layer, the portion of the molding layer vertically overlapping with the second mounting region of the first redistribution structure; and   a conductive bump structure contacting the conductive post through a through hole of the cover insulating layer, the conductive bump structure being configured to electrically connect the conductive post to the inter-package connector.   
     
     
         5 . The semiconductor package of  claim 4 , further comprising:
 a conductive adhesive layer between the conductive bump structure and the inter-package connector,   wherein the conductive adhesive layer includes gold (Au).   
     
     
         6 . The semiconductor package of  claim 1 , further comprising a heat dissipation plate attached to the top surface of the first semiconductor chip. 
     
     
         7 . The semiconductor package of  claim 1 , further comprising:
 an external connector attached to a lower portion of the first redistribution structure,   wherein the first redistribution pattern includes:
 a first conductive layer extending in the first redistribution insulating layer in the horizontal direction; 
 an external connection pad in contact with the external connector; and 
 a first conductive via pattern extending between the first conductive layer and the external connection pad, and 
   wherein the first conductive via pattern has a tapered shape having a horizontal width decreasing toward the external connection pad.   
     
     
         8 . The semiconductor package of  claim 7 , further comprising a seed metal layer between the first conductive via pattern and the external connection pad. 
     
     
         9 . The semiconductor package of  claim 1 , further comprising:
 a second redistribution structure on the molding layer, the second redistribution structure vertically overlapping with the second mounting region of the first redistribution structure and including a second redistribution insulating layer and a second redistribution pattern,   wherein the first semiconductor chip includes a first chip pad in a bottom surface thereof,   wherein the second semiconductor chip includes a second chip pad in a top surface thereof, and   wherein the second redistribution pattern electrically connects the conductive post to the second chip pad of the second semiconductor chip.   
     
     
         10 . The semiconductor package of  claim 9 , wherein the second redistribution pattern includes a second conductive via pattern passing through the second redistribution insulating layer and the molding layer and connected to the second chip pad of the second semiconductor chip. 
     
     
         11 . The semiconductor package of  claim 1 , wherein the first redistribution pattern includes:
 a first conductive layer extending in the horizontal direction in the first redistribution insulating layer; and   a first conductive via pattern extending between the first conductive layer and a first chip pad of the first semiconductor chip,   wherein the first conductive via pattern has a tapered shape having a horizontal width decreasing toward the first chip pad of the first semiconductor chip.   
     
     
         12 . A semiconductor package comprising:
 a first redistribution structure including a first mounting region and a second mounting region spaced apart from the first mounting region;   a first semiconductor chip mounted on the first mounting region of the first redistribution structure;   a molding layer contacting a top surface of the first redistribution structure and a side wall of the first semiconductor chip, and not covering a top surface of the first semiconductor chip;   a vertical connection conductor in the molding layer, the vertical connection conductor being electrically connected to the first semiconductor chip through a first redistribution pattern of the first redistribution structure; and   an upper semiconductor chip on the molding layer, the upper semiconductor chip vertically overlapping the vertical connection conductor in the second mounting region of the first redistribution structure and being electrically connected to the first semiconductor chip through the vertical connection conductor,   wherein the upper semiconductor chip does not vertically overlap the top surface of the first semiconductor chip, and   wherein no electronic components are disposed on the first mounting region between the top surface of the first semiconductor chip and an outside of the semiconductor package.   
     
     
         13 . The semiconductor package of  claim 12 , wherein the top surface of the first semiconductor chip is coplanar with a top surface of the molding layer and is exposed to the outside of the semiconductor package. 
     
     
         14 . The semiconductor package of  claim 12 , further comprising:
 a thermal conductive adhesive layer on the top surface of the first semiconductor chip; and   a heat dissipation plate on the thermal conductive adhesive layer.   
     
     
         15 . The semiconductor package of  claim 12 , further comprising:
 a cover insulating layer covering a portion of the molding layer, the portion of the molding layer vertically overlapping with the second mounting region of the first redistribution structure; and   a conductive bump structure in a through hole of the cover insulating layer, the conductive bump structure including a lower portion contacting the vertical connection conductor and an upper portion protruding from the cover insulating layer and being configured to electrically connect the vertical connection conductor to the upper semiconductor chip.   
     
     
         16 . The semiconductor package of  claim 12 , further comprising a dummy chip mounted on the second mounting region of the first redistribution structure. 
     
     
         17 . The semiconductor package of  claim 12 ,
 wherein a top surface of the molding layer is at a higher level than the top surface of the first semiconductor chip, and   wherein the molding layer includes a groove exposing the top surface of the first semiconductor chip.   
     
     
         18 . The semiconductor package of  claim 12 , further comprising:
 a second semiconductor chip mounted on the second mounting region of the first redistribution structure; and   a second redistribution structure on the molding layer, the second redistribution structure vertically overlapping with the second mounting region of the first redistribution structure and including a second redistribution insulating layer and a second redistribution pattern,   wherein the second semiconductor chip includes a second chip pad in a top surface thereof, and   wherein the second redistribution pattern electrically connects the vertical connection conductor and the second chip pad of the second semiconductor chip.   
     
     
         19 . The semiconductor package of  claim 12 ,
 wherein the first semiconductor chip is directly connected to the first redistribution structure, and   wherein the first redistribution structure further includes:
 a first redistribution insulating layer; 
 a first conductive layer extending in the first redistribution insulating layer in a horizontal direction; and 
 a first conductive via pattern passing through the first redistribution insulating layer in a vertical direction and electrically connecting the first conductive layer to a first chip pad of the first semiconductor chip, and 
   wherein the first conductive via pattern has a tapered shape having a horizontal width decreasing toward the first chip pad of the first semiconductor chip.   
     
     
         20 . A semiconductor package comprising:
 a lower package;   an upper package on the lower package;   a heat dissipation plate on the lower package; and   an inter-package connector between the lower package and the upper package,   wherein the lower package includes:
 a first redistribution structure including a first redistribution insulating layer and a first redistribution pattern; 
 a first semiconductor chip mounted on a first mounting region of the first redistribution structure; 
 a second semiconductor chip mounted on a second mounting region of the first redistribution structure, the second mounting region of the first redistribution structure being spaced apart from the first mounting region of the first redistribution structure; 
 a molding layer on the first redistribution structure and in contact with a side wall of the first semiconductor chip and a side wall of the second semiconductor chip; and 
 a conductive post on the second mounting region of the first redistribution structure, the conductive post passing through the molding layer; 
   wherein the heat dissipation plate is attached to a top surface of the first semiconductor chip,   wherein the upper package includes a third semiconductor chip electrically connected through the conductive post to at least one selected from a group consisting of the first semiconductor chip and the second semiconductor chip, and   wherein the upper package is spaced apart from the heat dissipation plate in a lateral direction parallel with the top surface of the molding layer and does not vertically overlap the top surface of the first semiconductor chip.