Phase locked loop architecture with reduced bandwidth variation

Abstract

Embodiments included herein are directed towards a phase-locked loop (PLL) circuit. Embodiments may include a phase frequency detector circuit configured to receive an input signal. Embodiments may further include a charge pump circuit configured to receive an output signal from the phase frequency detector circuit. The charge pump circuit may source or sink charge for a controlled amount of time based upon, at least in part, the output signal from the phase frequency detector circuit. The charge pump circuit may generate a current based upon, at least in part, a bandgap voltage, a switched capacitor resistor, and a frequency reference source. Embodiments may include a loop filter circuit configured to receive the current from the charge pump circuit and a voltage-controlled oscillator circuit configured to receive the current from the charge pump circuit. Embodiments may further include a feedback divider circuit operatively connected with the voltage-controlled oscillator circuit.

What is claimed is: 
     
         1 . A phase-locked loop (PLL) circuit comprising:
 a phase frequency detector circuit configured to receive an input signal;   a charge pump circuit configured to receive an output signal from the phase frequency detector circuit, wherein the charge pump circuit sources or sinks charge for a controlled amount of time-based upon, at least in part, the output signal from the phase frequency detector circuit, wherein the charge pump circuit generates a current based upon, at least in part, a bandgap voltage, a switched capacitor resistor, and a frequency reference source;   a loop filter circuit configured to receive the current from the charge pump circuit;   a voltage-controlled oscillator circuit configured to receive the current from the charge pump circuit;   a feedback divider circuit operatively connected with the voltage-controlled oscillator circuit; and   a complementary switched capacitor resistor in electrical communication with the switched capacitor resistor, wherein the switched capacitor resistor, the complementary switched capacitor resistor, a first capacitor, and a first transistor are operatively connected a common node.   
     
     
         2 . The phase-locked loop circuit of  claim 1 , wherein the phase-locked loop circuit is a dual path PLL having an integral path and a proportional path. 
     
     
         3 . The phase-locked loop circuit of  claim 2 , wherein the switched capacitor resistor is located in the proportional path. 
     
     
         4 . The phase-locked loop circuit of  claim 3 , further comprises:
 an RC filter circuit operatively connected with the switched capacitor resistor in the proportional path.   
     
     
         5 . The phase-locked loop circuit of  claim 1 , wherein the phase-locked loop circuit is a single path PLL. 
     
     
         6 . The phase-locked loop circuit of  claim 1 , wherein the loop filter circuit is configured to suppress high frequency components and transform a phase frequency detector output into the control signal. 
     
     
         7 . The phase-locked loop circuit of  claim 1 , wherein the voltage-controlled oscillator circuit uses an external voltage to influence its frequency of operation. 
     
     
         8 . The phase-locked loop circuit of  claim 1 , wherein the feedback divider circuit divides a voltage-controlled oscillator frequency and generates a feedback signal to the phase frequency detector circuit. 
     
     
         9 . The phase-locked loop circuit  claim 8 , wherein the feedback signal includes a waveform having a frequency lower than that of a voltage-controlled oscillator circuit output signal. 
     
     
         10 . A phase-locked loop (PLL) method comprising:
 providing a phase frequency detector circuit configured to receive an input signal;   receiving an output signal from the phase frequency detector circuit at a charge pump circuit, wherein the charge pump circuit sources or sinks charge for a controlled amount of time-based upon, at least in part, the output signal from the phase frequency detector circuit, wherein the charge pump circuit generates a current based upon, at least in part, a bandgap voltage, a switched capacitor resistor, and a frequency reference source;   receiving the current from the charge pump circuit at a loop filter circuit;   receiving the current from the charge pump circuit at a voltage-controlled oscillator circuit; and   operatively connecting a feedback divider circuit with the voltage-controlled oscillator circuit, wherein a complementary switched capacitor resistor is in electrical communication with the switched capacitor resistor, wherein the switched capacitor resistor, the complementary switched capacitor resistor, a first capacitor, and a first transistor are operatively connected a common node.   
     
     
         11 . The phase-locked loop circuit of  claim 10 , wherein the phase-locked loop circuit is a dual path PLL having an integral path and a proportional path. 
     
     
         12 . The phase-locked loop circuit of  claim 11 , wherein the switched capacitor resistor is located in the proportional path. 
     
     
         13 . The phase-locked loop circuit of  claim 12 , further comprising:
 an RC filter circuit operatively connected with the switched capacitor resistor in the proportional path.   
     
     
         14 . The phase-locked loop circuit of  claim 10 , wherein the phase-locked loop circuit is a single path PLL. 
     
     
         15 . The phase-locked loop circuit of  claim 10 , wherein the loop filter circuit is configured to suppress high frequency components and transform a phase frequency detector output into the control signal. 
     
     
         16 . The phase-locked loop circuit of  claim 10 , wherein the voltage-controlled oscillator circuit uses an external voltage to influence its frequency of operation. 
     
     
         17 . The phase-locked loop circuit of  claim 10 , wherein the feedback divider circuit divides a voltage-controlled oscillator frequency and generates a feedback signal to the phase frequency detector circuit. 
     
     
         18 . The phase-locked loop circuit  claim 17 , wherein the feedback signal includes a waveform having a frequency lower than that of a voltage-controlled oscillator circuit output signal.