Shared non-blocking crossbar buffer circuits and methods

Abstract

A circuit system includes a processing circuit, an accelerator circuit, and a buffer circuit that stores packets of data and that is coupled to the processing circuit and to the accelerator circuit. The buffer circuit functions as a crossbar circuit by allowing each of the accelerator circuit and the processing circuit to access at least one of the packets of data stored in the buffer circuit during access to another one of the packets of data stored in the buffer circuit.

What is claimed is: 
     
         1 . A circuit system comprising:
 a processing circuit;   an accelerator circuit; and   a buffer circuit that stores packets of data and that is coupled to the processing circuit and to the accelerator circuit, wherein the buffer circuit functions as a crossbar circuit by allowing the accelerator circuit and the processing circuit to access first ones of the packets of data stored in the buffer circuit during access to a second one of the packets of data stored in the buffer circuit, wherein the buffer circuit allows the accelerator circuit and the processing circuit to access a third one of the packets of data stored in the buffer circuit at different times without blocking.   
     
     
         2 . The circuit system of  claim 1 , wherein the processing circuit comprises programmable logic circuits configurable to perform custom logic functions using the packets of data. 
     
     
         3 . The circuit system of  claim 1 , wherein the accelerator circuit accelerates security functions for the circuit system using at least one of the packets of data. 
     
     
         4 . The circuit system of  claim 1 , wherein the accelerator circuit is a configurable logic integrated circuit. 
     
     
         5 . The circuit system of  claim 1 , wherein the buffer circuit allows the accelerator circuit and the processing circuit to access any of the packets of data stored in the buffer circuit. 
     
     
         6 . The circuit system of  claim 1 , wherein the buffer circuit allows the processing circuit to access only a portion of each of the packets of data stored in the buffer circuit. 
     
     
         7 . The circuit system of  claim 6 , wherein the buffer circuit stores headers for the packets of data, and wherein the buffer circuit allows the processing circuit to access the headers. 
     
     
         8 . The circuit system of  claim 1 , wherein the buffer circuit stores handles that identify the packets of data, and wherein the processing circuit and the accelerator circuit access the packets of data stored in the buffer circuit based on the handles. 
     
     
         9 . The circuit system of  claim 1 , wherein the buffer circuit is a non-blocking crossbar buffer circuit. 
     
     
         10 . A method for accessing buffer circuit in a circuit system, the method comprising:
 accessing at least a portion of a first packet of data stored in the buffer circuit during a first data access using a processing circuit in the circuit system;   performing a first function with the processing circuit using the portion of the first packet of data accessed from the buffer circuit;   accessing at least a portion of a second packet of data stored in the buffer circuit during a second data access using an accelerator circuit in the circuit system concurrently with the first data access;   performing a second function with the accelerator circuit using the portion of the second packet of data accessed from the buffer circuit; and   allowing the accelerator circuit and the processing circuit to access a third packet of data stored in the buffer circuit at different times without blocking.   
     
     
         11 . The method of  claim 10  further comprising:
 accessing at least a portion of a fourth packet of data stored in the buffer circuit during a third data access using a device external to the circuit system; and 
 performing a third function with the device using the portion of the fourth packet of data accessed from the buffer circuit. 
 
     
     
         12 . The method of  claim 10 , wherein the buffer circuit is a crossbar buffer circuit. 
     
     
         13 . The method of  claim 10 , wherein accessing at least the portion of the first packet of data during the first data access comprises accessing a first header, and wherein performing the first function comprises performing the first function with the processing circuit using the first header. 
     
     
         14 . The method of  claim 10 , wherein accessing at least the portion of the first packet of data during the first data access comprises accessing the portion of the first packet of data using a handle that identifies the first packet of data. 
     
     
         15 . The method of  claim 14 , wherein performing the first function with the processing circuit comprises performing the first function using the handle. 
     
     
         16 . A circuit system comprising:
 programmable logic circuits; and   a crossbar buffer circuit, wherein a first one of the programmable logic circuits is configurable to access at least a portion of a first packet of data stored in the crossbar buffer circuit during a first data access, wherein a second one of the programmable logic circuits is configurable to access at least a portion of a second packet of data stored in the crossbar buffer circuit during a second data access concurrently with the first data access,   wherein the crossbar buffer circuit allows the first one of the programmable logic circuits to access only the portion of the first packet of data stored in the crossbar buffer circuit, and wherein the crossbar buffer circuit allows the second one of the programmable logic circuits to access only the portion of the second packet of data stored in the crossbar buffer circuit.   
     
     
         17 . The circuit system of  claim 16 , wherein the programmable logic circuits and the crossbar buffer circuit are coupled together within an integrated circuit die. 
     
     
         18 . The circuit system of  claim 16  further comprising:
 an accelerator circuit that accelerates functions for the circuit system, wherein the accelerator circuit is configurable to access at least a portion of a third packet of data stored in the crossbar buffer circuit during a third data access concurrently with the first data access. 
 
     
     
         19 . The circuit system of  claim 16 , wherein the first one of the programmable logic circuits is configurable to perform a first function using the portion of the first packet of data accessed from the crossbar buffer circuit, and
 wherein the second one of the programmable logic circuits is configurable to perform a second function using the portion of the second packet of data accessed from the crossbar buffer circuit.   
     
     
         20 . The circuit system of  claim 16 , wherein the first one of the programmable logic circuits is configurable to access at least the portion of the first packet of data during the first data access using a first handle that identifies the first packet of data, and
 wherein the second one of the programmable logic circuits is configurable to access at least the portion of the second packet of data during the second data access using a second handle that identifies the second packet of data.