Non-standard bus controller-based programmable logic device (PLD) architecture for interconnecting multiple bus controllers and increased numbers of PLD modules

Abstract

A bus controller-based programmable logic device (PLD) architecture is provided and includes a dual-port unit interposed between bus controllers. The dual port unit includes first and second data transfer layers. The first data transfer layer includes write and read areas for data transfer between the first and second bus controllers, respectively. A write to the read area is prevented during a read by the second bus controller. The second data transfer layer includes read and write areas for data transfer between the first and second bus controllers, respectively. A write to the read area is prevented during a read by the first bus controller.

What is claimed is: 
     
         1 . A bus controller-based programmable logic device (PLD) architecture, comprising:
 a dual-port unit interposed between first and second bus controllers and comprising:
 a first data transfer layer comprising write and read areas for data transfer between the first and second bus controllers, respectively, and a data transfer control unit interposed between the write area and the read area and configured to prevent writing of data to the read area of the first data transfer layer, from the write area, during reading from the read area by the second bus controller; and 
 a second data transfer layer comprising read and write areas for data transfer between the first and second bus controllers, respectively, and a data transfer control unit interposed between the read area and the write area and configured to prevent writing of data to the read area of the second data transfer layer, from the write area, during reading from the read area by the first bus controller. 
   
     
     
         2 . The bus controller-based PLD architecture according to  claim 1 , further comprising thirty-one or more PLD modules, wherein command sequence execution by the first and second bus controllers is triggered by one of the PLD modules. 
     
     
         3 . The bus controller-based PLD architecture according to  claim 1 , wherein data is transferred along the first and second data transfer layers simultaneously. 
     
     
         4 . The bus controller-based PLD architecture according to  claim 1 , wherein:
 the data transfer control unit of the first data transfer layer is further configured to write data, which is prevented from being written to the read area of the first data transfer layer during the reading by the second bus controller, to the write area of the first data transfer layer during the reading by the second bus controller, and   the data transfer control unit of the second data transfer layer is further configured to write data, which is prevented from being written to the read area of the second data transfer layer during the reading by the first bus controller, to the write area of the second data transfer layer during the reading by the first bus controller.   
     
     
         5 . The bus controller-based PLD architecture according to  claim 4 , wherein:
 the data transfer control unit of the first data transfer layer is further configured to mirror data in one system clock, which is written to the write area of the first data transfer layer, to the read area of the first data transfer layer following the reading by the second bus controller, and   the data transfer control unit of the second data transfer layer is further configured to mirror data in one system clock, which is written to the write area of the second data transfer layer, to the read area of the second data transfer layer following the reading by the first bus controller.   
     
     
         6 . A bus controller-based programmable logic device (PLD) architecture, comprising:
 PLD modules;   first and second bus controllers each responsive to a trigger by one of the PLD modules; and   a dual-port unit interposed between the first and second bus controllers and comprising:
 a first data transfer layer comprising write and read areas for data transfer between the first and second bus controllers, respectively, and a data transfer control unit interposed between the write area and the read area and configured to prevent writing of data to the read area of the first data transfer layer, from the write area, during reading from the read area by the second bus controller; and 
 a second data transfer layer comprising read and write areas for data transfer between the first and second bus controllers, respectively, and a data transfer control unit interposed between the read area and the write area and configured to prevent writing of data to the read area of the second data transfer layer, from the write area, during reading from the read area by the first bus controller. 
   
     
     
         7 . The bus controller-based PLD architecture according to  claim 6 , wherein the PLD modules comprise up to thirty-one or more PLD modules. 
     
     
         8 . The bus controller-based PLD architecture according to  claim 6 , wherein each of the first and second bus controllers comprises control logic, interface logic, input multiplexing logic and memory. 
     
     
         9 . The bus controller-based PLD architecture according to  claim 6 , wherein data is transferred along the first and second data transfer layers simultaneously. 
     
     
         10 . The bus controller-based PLD architecture according to  claim 6 , wherein:
 the data transfer control unit of the first data transfer layer is further configured to write data, which has been prevented from being written to the read area of the first data transfer layer during the read by the second bus controller, to the write area of the first data transfer layer during the reading by the second bus controller, and   the data transfer control unit of the second data transfer layer is further configured to write data, which has been prevented from being written to the read area of the second data transfer layer during the read by the first bus controller, to the write area of the second data transfer layer during the reading by the first bus controller.   
     
     
         11 . The bus controller-based PLD architecture according to  claim 10 , wherein:
 the data transfer control unit of the first data transfer layer is further configured to mirror data in one system clock, which has been written to the write area of the first data transfer layer, to the read area of the first data transfer layer subsequent to the read by the second bus controller, and   the data transfer control unit of the second data transfer layer is further configured to mirror data in one system clock, which has been written to the write area of the second data transfer layer, to the read area of the second data transfer layer subsequent to the read by the first bus controller.   
     
     
         12 . A method of operating a bus controller-based programmable logic device (PLD) architecture comprising PLD modules and first and second bus controllers, the method comprising:
 receiving a trigger from one of the PLD modules at one of the first and second bus controllers; and   executing a command sequence by the one of the first and second bus controllers by exchanging data between the first and second bus controllers across a dual-port unit comprising first and second data transfer layers,   the exchanging of the data comprising:
 reading, from a read area of the first data transfer layer, by the second bus controller and preventing writing of data to the read area of the first data transfer layer, from the write area, during the reading from the read area by the second bus controller by a data transfer control unit of the first data transfer layer, which is interposed between the write area and the read area; and 
 reading, from a read area of the second data transfer layer, by the first bus controller and preventing writing of data to the read area of the second data transfer layer, from the write area, during the reading from the read area by the first bus controller by a data transfer control unit of the second data transfer layer, which is interposed between the read area and the write area. 
   
     
     
         13 . The method according to  claim 12 , wherein the PLD modules comprise up to thirty-one or more PLD modules. 
     
     
         14 . The method according to  claim 12 , wherein each of the first and second bus controllers comprises control logic, interface logic, input multiplexing logic and memory. 
     
     
         15 . The method according to  claim 12 , wherein data is transferred along the first and second data transfer layers simultaneously. 
     
     
         16 . The method according to  claim 12 , wherein the method further comprises:
 writing data, which has been prevented from being written to the read area of the first data transfer layer during the reading by the second bus controller, to the write area of the first data transfer layer by the data transfer control unit of the first data transfer layer during the reading by the second bus controller, and   writing data, which has been prevented from being written to the read area of the second data transfer layer during the reading by the first bus controller, to the write area of the second data transfer layer by the data transfer control unit of the second data transfer layer during the reading by the first bus controller.   
     
     
         17 . The method according to  claim 16 , wherein the method further comprises:
 mirroring data in one system clock, which has been written to the write area of the first data transfer layer, to the read area of the first data transfer layer by the data transfer control unit of the first data transfer layer subsequent to the reading by the second bus controller, and   mirroring data in one system clock, which has been written to the write area of the second data transfer layer, to the read area of the second data transfer layer by the data transfer control unit of the second data transfer layer subsequent to the reading by the first bus controller.