Converter for converting data type, chip, electronic device, and method therefor

Abstract

A converter for data type conversion includes a first conversion stage and a second conversion stage. The first conversion stage is configured to receive first type data and first descriptive information about the first type data, and according to the first descriptive information, convert the first type data into an intermediate result. The second conversion stage is configured to receive second descriptive information about second type data, and according to the second descriptive information, convert the intermediate result into the second type data. A method for data type conversion includes: receiving first type data and first descriptive information about the first type data, and according to the first descriptive information, converting the first type data into an intermediate result; and receiving second descriptive information about second type data, and according to the second descriptive information, converting the intermediate result into the second type data.

What is claimed: 
     
         1 . A converter for data type conversion, comprising:
 a first conversion stage (L 1 ) configured to receive first type data and first descriptive information about the first type data, and according to the first descriptive information convert the first type data into an intermediate result; and   a second conversion stage (L 2 ) configured to receive second descriptive information about second type data, and according to the second descriptive information, convert the intermediate result into the second type data,   wherein the first conversion stage (L 1 ) includes a first receiving unit (Rx 1 ) and a first extracting unit (E 1 ), and the first descriptive information includes a first data type of the first type data and a first exponent bit of the first type data, wherein
 the first receiving unit (Rx 1 ) is configured to receive the first type data and the first descriptive information; and 
 the first extracting unit (E 1 ) is configured to, from the first type data and the first descriptive information, extract an intermediate sign bit (Msign), an intermediate data bit (Mdata), and an intermediate exponent bit (Mshift) as the intermediate result, 
   wherein the second conversion stage (L 2 ) includes a second calculation unit (C 2 ), a second pre-output parsing unit (P 2 ), and a second data recovery unit (R 2 ), wherein
 the second calculation unit (C 2 ) is configured to receive the intermediate result and the second descriptive information, and according to the intermediate result and the second descriptive information, calculate a second intermediate result; 
 the second pre-output parsing unit (P 2 ) is configured to calculate a pre-output data bit (Pdata) and a pre-output sign bit (Psign) according to the second intermediate result; and 
 the second data recovery unit (R 2 ) is configured to generate the second type data according to the pre-output data bit (Pdata) and the pre-output sign bit (Psign). 
   
     
     
         2 . The converter of  claim 1 , wherein the second descriptive information includes a second data type of the second type data and a second exponent bit (Sshift) of the second type data, and the second calculation unit (C 2 ) includes:
 an absolute value calculation circuit (C 21 ) configured to calculate a second intermediate data bit (ABS) according to the intermediate data bit (Mdata);   a sign bit calculation circuit (C 22 ) configured to calculate a second intermediate sign bit (Sign) according to the intermediate sign bit (Msign); and   a difference exponent bit calculation circuit (C 23 ) configured to calculate a difference exponent bit (Dshift) between the intermediate exponent bit (Mshift) and the second exponent bit (Sshift) as a second intermediate exponent bit (EXP).   
     
     
         3 . The converter of  claim 2 , wherein the second calculation unit (C 2 ) further includes:
 a rounding bit calculation circuit (C 24 ) configured to calculate a second intermediate rounding bit (STK) according to the second intermediate data bit (ABS) and the second intermediate sign bit (Sign).   
     
     
         4 . The converter of  claim 3 , wherein the rounding bit calculation circuit (C 24 ) is implemented by an AND-OR logic. 
     
     
         5 . The converter of  claim 3 , wherein the second pre-output parsing unit (P 2 ) is configured to calculate the pre-output data bit (Pdata) and the pre-output sign bit (Psign) according to the second intermediate data bit (ABS), the second intermediate sign bit (Sign), the second intermediate exponent bit (EXP), and the second intermediate rounding bit (STK). 
     
     
         6 . The converter of  claim 5 , wherein the second pre-output parsing unit (P 2 ) includes: a shift operator (P 21 ) and an adder (P 22 ), and the second pre-output parsing unit (P 2 ) is configured to generate a temporary output data bit (ABS′) and the pre-output sign bit (Psign), wherein
 the shift operator (P 21 ) is configured to shift the second intermediate data bit (ABS) by the second intermediate exponent bit (EXP) to obtain a shift result; 
 the adder (P 22 ) is configured to generate the temporary output data bit (ABS′) according to the shift result and the second intermediate rounding bit (STK); and 
 the pre-output sign bit (Psign) is equal to the second intermediate sign bit (Sign). 
 
     
     
         7 . The converter of  claim 6 , wherein the pre-output parsing unit (P 2 ) further includes a selector (P 23 ), wherein the selector (P 23 ) is configured to detect whether the temporary output data bit (ABS′) is greater than a saturation value,
 if the temporary output data bit (ABS′) is greater than the saturation value, the selector (P 23 ) performs saturation processing on the temporary output data bit (ABS′) to obtain the pre-output data bit (Pdata); and 
 if the temporary output data bit (ABS′) is not greater than the saturation value, the selector (P 23 ) outputs the temporary output data bit (ABS′) as the pre-output data bit (Pdata). 
 
     
     
         8 . The converter of  claim 5 , wherein the second data recovery unit (R 2 ) includes a pre-output processing circuit (R 21 ) and a data assembly circuit (R 22 ), wherein
 the pre-output processing circuit (R 21 ) is configured to receive the pre-output data bit (Pdata) and the pre-output sign bit (Psign) to generate an output data bit representation (Data_out); and   the data assembly circuit (R 22 ) is configured to generate the second type data according to the output data bit representation (Data_out) and the pre-output sign bit Psign,   wherein the pre-output processing circuit (R 21 ) is further configured to generate a floating-point number decimal point bit representation (SHIFT_FP), and the data assembly circuit (R 22 ) is configured to generate the second type data according to the output data bit representation (Data_out), the floating-point number decimal point bit representation (Shift_FP), and the pre-output sign bit (Psign).   
     
     
         9 . The converter of  claim 8 , wherein the pre-output processing circuit (R 21 ) includes: a fourth selector and a second complement calculator, wherein
 the fourth selector is configured to receive the pre-output data bit (Pdata) and the pre-output sign bit (Psign), wherein if the pre-output sign bit (Psign) is a negative number, the fourth selector outputs the pre-output data bit to the second complement calculator, and if the pre-output sign bit (Psign) is a positive number or is not the negative number, the fourth selector outputs the pre-output data bit as the output data bit representation (Data_out); and   the second complement calculator is configured to calculate a complement for the pre-output data bit (Pdata),   wherein the pre-output processing circuit (R 21 ) further includes: a third selector, a second normalizer, and a floating-point number decimal point location determinator, wherein   the third selector is configured to receive the pre-output data bit (Pdata) and judge whether a data type of the pre-output data bit (Pdata) is a first type or a second type, wherein if the data type of the pre-output data bit (Pdata) is the first type, the third selector sends the pre-output data bit (Pdata) to the fourth selector, and if the data type of the pre-output data bit (Pdata) is the second type, the third selector sends the pre-output data bit (Pdata) to the second normalizer;   the second normalizer is configured to normalize the pre-output data bit (Pdata) and output a normalized pre-output data bit (Pdata) as the output data bit representation (Data_out); and   the floating-point number decimal point location determinator is configured to determine the floating-point number decimal point bit representation (SHIFT_FP) according to an output of the second normalizer.   
     
     
         10 . The converter of  claim 2 , wherein the second calculation unit (C 2 ) further includes:
 a rounding bit calculation circuit (C 24 ) configured to calculate a second intermediate rounding bit (STK) according to the second intermediate data bit (ABS), the second intermediate exponent bit (EXP), and the second intermediate sign bit (Sign).   
     
     
         11 . The converter of  claim 2 , wherein the absolute value calculation circuit (C 21 ) includes:
 a second selector configured to judge whether the intermediate data bit (Mdata) is less than 0; and   a first complement calculator configured to calculate a complement of the intermediate data bit (Mdata) as the second intermediate data bit (ABS) if the intermediate data bit (Mdata) is less than 0, otherwise,   take the intermediate data bit (Mdata) as the second intermediate data bit (ABS).   
     
     
         12 . The converter of  claim 11 , wherein the absolute value calculation circuit (C 21 ) further includes a first selector and a first normalizer, wherein
 the first selector is configured to judge whether a data type of the intermediate data bit (Mdata) is a first type or a second type;   if the data type of the intermediate data bit (Mdata) is the first type, the first selector selects the second selector for processing;   if the data type of the intermediate data bit (Mdata) is the second type, the first selector selects the first normalizer for processing; and   the first normalizer is configured to normalize the intermediate data bit (Mdata) as the second intermediate data bit (ABS) if the data type of the intermediate data bit (Mdata) is the second type.   
     
     
         13 . The converter of  claim 2 , wherein
 the sign bit calculation circuit (C 22 ) is a straight connection line.   
     
     
         14 . The converter of  claim 2 , wherein the second pre-output parsing unit (P 2 ) includes:
 a rounding bit calculation circuit (C 24 ) configured to calculate a second intermediate rounding bit (STK) according to the second intermediate data bit (ABS), the second intermediate exponent bit (EXP), and the second intermediate sign bit (Sign).   
     
     
         15 . The converter of  claim 1 , wherein the first extracting unit (E 1 ) includes: a sign bit calculation circuit (E 11 ), a significant bit calculation circuit (E 12 ), and an intermediate exponent bit calculation circuit (E 13 ), wherein
 the sign bit calculation circuit (E 11 ) is configured to, from the first type data, extract a sign of the first type data as the intermediate sign bit (Msign);   the significant bit calculation circuit (E 12 ) is configured to, from the first type data, extract a significant data bit of the first type data as the intermediate data bit (Mdata); and   the intermediate exponent bit calculation circuit (E 13 ) is configured to, according to the first type data or the first exponent bit, obtain exponent information of the first type data as the intermediate exponent bit (Mshift).   
     
     
         16 . The converter of  claim 1 , further comprising a memory configured to store the intermediate result. 
     
     
         17 . A method for data type conversion, comprising:
 receiving, by a first conversion stage (L 1 ), first type data and first descriptive information about the first type data, and according to the first descriptive information, converting the first type data into an intermediate result; and   receiving, by a second conversion stage (L 2 ), second descriptive information about second type data, and according to the second descriptive information, converting the intermediate result into the second type data,   wherein the first conversion stage (L 1 ) includes a first receiving unit (Rx 1 ) and a first extracting unit (E 1 ), and the first descriptive information includes a first data type of the first type data and a first exponent bit of the first type data, wherein
 the first receiving unit (Rx 1 ) is configured to receive the first type data and the first descriptive information; and 
 the first extracting unit (E 1 ) is configured to, from the first type data and the first descriptive information, extract an intermediate sign bit (Msign), an intermediate data bit (Mdata), and an intermediate exponent bit (Mshift) as the intermediate result, 
   wherein the second conversion stage (L 2 ) includes a second calculation unit (C 2 ), a second pre-output parsing unit (P 2 ), and a second data recovery unit (R 2 ), wherein
 the second calculation unit (C 2 ) is configured to receive the intermediate result and the second descriptive information, and according to the intermediate result and the second descriptive information, calculate a second intermediate result; 
 the second pre-output parsing unit (P 2 ) is configured to calculate a pre-output data bit (Pdata) and a pre-output sign bit (Psign) according to the second intermediate result; and 
 the second data recovery unit (R 2 ) is configured to generate the second type data according to the pre-output data bit (Pdata) and the pre-output sign bit (Psign).