Feedback-based clock frequency adjustment for dynamic clock voltage scaling

Abstract

An apparatus, including: a set of one or more cores; a processor configured to generate a proposed frequency of a clock signal provided to the set of one or more cores in accordance with a dynamic clock voltage scaling (DCVS); a feedback-based clock frequency adjuster configured to generate an adjustment frequency based on feedback information from the set of one or more cores; and a clock generator configured to generate the clock signal with an effective frequency based on the proposed frequency and the adjustment frequency.

What is claimed: 
     
         1 . An apparatus, comprising:
 a set of one or more cores;   a processor configured to generate a proposed frequency of a clock signal provided to the set of one or more cores in accordance with a dynamic clock voltage scaling (DCVS);   a feedback-based clock frequency adjuster configured to generate an adjustment frequency based on feedback information from the set of one or more cores; and   a clock generator configured to generate the clock signal with an effective frequency based on the proposed frequency and the adjustment frequency;   wherein the feedback-based clock frequency adjuster is configured to generate the adjustment frequency based on the feedback information in response to the proposed frequency being less than a defined constant of less than one multiplied by a maximum frequency available for the set of one or more cores, and   wherein the defined constant defines a confidence level for the proposed frequency of a clock signal relative to the maximum frequency.   
     
     
         2 . The apparatus of  claim 1 , wherein the feedback information is based on instructions per cycle executed by the set of one or more cores. 
     
     
         3 . The apparatus of  claim 1 , wherein the feedback information indicates whether an operation of the set of one or more cores is execution bound or memory bound. 
     
     
         4 . The apparatus of  claim 3 , wherein the operation of the set of one or more cores is execution bound if a majority of data to be processed is in the set of one or more cores. 
     
     
         5 . The apparatus of  claim 3 , wherein the operation of the set of one or more cores is memory bound if a majority of data to be processed by the set of one or more cores resides in memory to be transferred to the set of one or more cores. 
     
     
         6 . The apparatus of  claim 1 , wherein the set of one or more cores includes a set of one or more instruction counters configured to generate the feedback information. 
     
     
         7 . The apparatus of  claim 1 , wherein the feedback information is based on one or more percent changes of instructions per cycle (IPC) executed by the set of one or more cores over one or more time intervals, respectively. 
     
     
         8 . The apparatus of  claim 1 , wherein the clock generator is configured to set the effective frequency of the clock signal above the proposed frequency based on the adjustment frequency. 
     
     
         9 . The apparatus of  claim 8 , wherein the clock generator is configured to set the effective frequency of the clock signal to a maximum frequency available for the set of one or more cores. 
     
     
         10 . The apparatus of  claim 8 , wherein the feedback-based clock frequency adjuster is configured to generate the adjustment frequency in response to the feedback information indicating an operation of the set of one or more cores being execution bound. 
     
     
         11 . The apparatus of  claim 1 , wherein the feedback-based clock frequency adjuster is configured to generate the adjustment frequency based on the proposed frequency. 
     
     
         12 . The apparatus of  claim 1 , wherein the feedback-based clock frequency adjuster is configured to generate the adjustment frequency based on a maximum frequency available for the set of one or more cores. 
     
     
         13 . The apparatus of  claim 1 , wherein the feedback-based clock frequency adjuster is configured to not generate the adjustment frequency based on the proposed frequency being greater than the defined constant multiplied by the maximum frequency available for the set of one or more cores. 
     
     
         14 . The apparatus of  claim 1 , wherein the feedback-based clock frequency adjuster is configured to generate the adjustment frequency based on a current effective frequency of the clock signal being greater than a defined constant multiplied by a current proposed frequency. 
     
     
         15 . The apparatus of  claim 1 , wherein the processor is configured to generate the proposed frequency based on a set of one or more previous effective frequency of the clock signal. 
     
     
         16 . The apparatus of  claim 1 , wherein the processor is configured to generate the proposed frequency based on an estimated task load on the set of one or more cores. 
     
     
         17 . The apparatus of  claim 1 , wherein the processor is configured to run an operating system (OS), and wherein the proposed frequency comprises an operating system (OS) proposed frequency. 
     
     
         18 . The apparatus of  claim 1 , wherein the clock generator is configured to reduce the effective frequency of the clock signal in response to a temperature associated with the set of one or more cores exceeding a threshold. 
     
     
         19 . The apparatus of  claim 1 , wherein the clock generator is configured to reduce the effective frequency of the clock signal in response to a power consumption of or a current drawn by the set of one or more cores exceeding a threshold. 
     
     
         20 . A method, comprising:
 generating a proposed frequency for a clock signal;   generating a frequency adjustment based on feedback information received from a set of one or more cores in response to the proposed frequency being less than a defined constant of less than one multiplied by a maximum frequency available for the set of one or more cores;   generating a clock signal with an effective frequency based on the proposed frequency and the frequency adjustment; and   providing the clock signal to the set of one or more cores,   wherein the defined constant defines a confidence level for the proposed frequency of a clock signal relative to the maximum frequency.   
     
     
         21 . The method of  claim 20 , wherein the feedback information is based on instructions per cycle executed by the set of one or more cores. 
     
     
         22 . The method of  claim 20 , wherein the feedback information indicates whether an operation of the set of one or more cores is execution bound. 
     
     
         23 . The method of  claim 20 , further comprising increasing the effective frequency of the clock signal above the proposed frequency in response to the frequency adjustment being generated based on the feedback information indicating that an operation of the set of one or more cores is execution bound. 
     
     
         24 . The method of  claim 20 , further comprising setting the effective frequency of the clock signal to the proposed frequency in response to the frequency adjustment not being generated based on the feedback information indicating that an operation of the set of one or more cores is not execution bound. 
     
     
         25 . An apparatus, comprising:
 means for generating a proposed frequency for a clock signal;   means for generating a frequency adjustment based on feedback information received from a set of one or more cores in response to the proposed frequency being less than a defined constant of less than one multiplied by a maximum frequency available for the set of one or more cores;   means for generating a clock signal with an effective frequency based on the proposed frequency and the frequency adjustment; and   means for providing the clock signal to the set of one or more cores,   wherein the defined constant defines a confidence level for the proposed frequency of a clock signal relative to the maximum frequency.   
     
     
         26 . The apparatus of  claim 25 , wherein the feedback information is based on instructions per cycle executed by the set of one or more cores. 
     
     
         27 . The apparatus of  claim 25 , wherein the feedback information indicates whether an operation of the set of one or more cores is execution bound. 
     
     
         28 . The apparatus of  claim 25 , further comprising means for increasing the effective frequency of the clock signal above the proposed frequency in response to the frequency adjustment being generated based on the feedback information indicating that an operation of the set of one or more cores is execution bound. 
     
     
         29 . The apparatus of  claim 25 , further comprising means for setting the effective frequency of the clock signal to the proposed frequency in response to the frequency adjustment not being generated based on the feedback information indicating that an operation of the set of one or more cores is not execution bound.