Quantum simulation

Abstract

A method for reducing computation time while simulating quantum computation on a classical computer by performing an algorithm used to determine the most efficient input contraction, the method including receiving, by a processor, a tensor network representing a quantum circuit, computing, by the processor, an ordering for the tensor network by an ordering algorithm, contracting, by the processor, the tensor network by eliminating indices according to the ordering resulting in a contracted tensor network, and returning, by the processor, the contracted tensor network.

What is claimed is: 
     
         1 . A method for reducing computation time while simulating quantum computation on a classical computer by performing an algorithm used to determine a most efficient input contraction, the method comprising:
 receiving, by a processor, a read-in of a quantum approximate optimization algorithm (QAOA) circuit having a first plurality of gates;   reduce, by a gate-optimizing system, gates in the QAOA circuit to a second plurality of gates which is less than the first plurality of gates;   represent the QAOA having the second plurality of gates as a tensor network;   computing, by the processor, an ordering for the tensor network by an ordering algorithm;   contracting, by the processor, the tensor network by eliminating indices according to the ordering resulting in a contracted tensor network; and   returning, by the processor, the contracted tensor network.   
     
     
         2 . The method of  claim 1 , wherein iterating, by the processer, only removes indices with highest number of connected nodes from the tensor network. 
     
     
         3 . The method of  claim 1 , wherein a contraction index order that provides the lowest contraction width is stored in a contraction schedule in a nontransitory computer readable medium for reuse in simulating different circuit parameters. 
     
     
         4 . The method of  claim 1 , wherein ZZ gates and diagonal gates are used to simplify the tensor network. 
     
     
         5 . The method of  claim 1 , wherein the contraction order is found using tree decomposition. 
     
     
         6 . The method of  claim 1 , wherein light cone optimization is employed prior to contracting the tensor network, such that only gates of the quantum circuit that affect solution are used. 
     
     
         7 . The method of  claim 1 , wherein the ordering algorithm is a greedy algorithm, a randomized greedy algorithm, or a heuristic solver. 
     
     
         8 . The method of  claim 1 , wherein a contraction of the tensor network is a merged index contraction. 
     
     
         9 . A system for reducing computation time while simulating quantum computation on a classical computer by performing an algorithm used to determine the most efficient input contraction, the system comprising:
 a computer comprising a processor and a memory, wherein the processor is set up to perform operations, embodied in instructions on computer readable medium, to:
 receive a read-in of a quantum approximate optimization algorithm (QAOA) circuit having a first plurality of gates; 
 reduce, by a gate-optimizing system, gates in the QAOA circuit to a second plurality of gates which is less than the first plurality of gates; 
 represent the QAOA having the second plurality of gates as a tensor network; 
 optimize tensor network through implementation of diagonal gates; 
 compute an index contraction ordering for the tensor network; 
 merge a portion of indices of the tensor network to contract the tensor network according to the index contraction ordering; 
 compute a contracted tensor network; and 
 return the contracted tensor network. 
   
     
     
         10 . The system of  claim 9 , wherein the processor only removes indices with highest number of connected vertices from the tensor network. 
     
     
         11 . The system of  claim 9 , wherein the lowest contraction width is stored in a contraction schedule in a nontransitory computer readable medium for reuse in simulating different circuit parameters. 
     
     
         12 . The system of  claim 9 , wherein the ordering is determined by a greedy ordering algorithm, a randomized greedy ordering algorithm, or a heuristic solver. 
     
     
         13 . The system of  claim 9 , further comprising optimizing the tensor network prior to computing an ordering by use of ZZ gates. 
     
     
         14 . The system of  claim 9 , wherein the contraction order is found using tree decomposition. 
     
     
         15 . The system of  claim 9 , wherein the gate optimization system utilizes light cone optimization is employed such that only a gates of the quantum circuit that affect solution are used.