Buried channel transistor structures and processes

Abstract

Transistors include trenches formed in the semiconductor substrate having a first conductive type. The trenches define, in a channel width plane of the transistor, at least one nonplanar substrate structure having a plurality of sidewall portions and a tip portion disposed between the plurality of sidewall portions. An epitaxial overlayer is epitaxially grown on the sidewall portions and the tip portion. A channel doping layer having a doped portion of the semiconductor substrate is formed in the nonplanar substrate structure and enclosed by the epitaxial overlayer. An isolation layer is disposed in the trenches and over the epitaxial overlayer. A gate is disposed on the isolation layer and extends into the trenches.

What is claimed is: 
     
         1 . A transistor formed in a semiconductor substrate, comprising:
 a plurality of trenches formed in the semiconductor substrate having a first conductive type, the plurality of trenches defining, in the semiconductor substrate, in a channel width plane of the transistor, a nonplanar substrate structure comprising a plurality of sidewall portions and a tip portion disposed between the plurality of sidewall portions,   an epitaxial overlayer comprising an overlayer material epitaxially grown within the plurality of trenches and on the plurality of sidewall portions and the tip portion of the nonplanar substrate structure;   a channel doping layer comprising a doped portion of the semiconductor substrate formed in the nonplanar substrate structure and enclosed by the epitaxial overlayer, wherein the channel doping layer is implanted into the plurality of sidewall portions and the tip portion of the nonplanar substrate structure, wherein the channel doping layer is a square wave shape that encloses the tip portion and at least partially encloses the plurality of sidewall portions of the nonplanar substrate structure, wherein the square wave shape of the channel doping layer conforms to the nonplanar substate structure, and wherein a bottom of the square wave shape terminates at a same depth as the isolation layer;   an isolation layer disposed in the plurality of trenches and over the epitaxial overlayer; and   a gate disposed on the isolation layer and extending into the plurality of trenches;   wherein the isolation layer and epitaxial overlayer are arranged to physically separate the channel doping layer from the gate.   
     
     
         2 . The transistor of  claim 1 , wherein the epitaxial overlayer has a thickness between the isolation layer and channel doping layer of five nanometers to thirty nanometers. 
     
     
         3 . The transistor of  claim 2 , wherein the channel doping layer has a second thickness of one nanometer to ten nanometers. 
     
     
         4 . The transistor of  claim 1 , wherein the epitaxial overlayer and the channel doping layer have a shape that follows a profile of the nonplanar substrate structure in the channel width plane. 
     
     
         5 . The transistor of  claim 1 , wherein the overlayer material is a same material as the semiconductor substrate. 
     
     
         6 . The transistor of  claim 1 , wherein the epitaxial overlayer is a first epitaxial overlayer,
 wherein the channel doping layer comprises a second epitaxial overlayer formed of an in situ epitaxially grown overlayer doped with a dopant having a second conductive type which is opposite the first conductive type,   wherein the first epitaxial overlayer is disposed on the second epitaxial overlayer.   
     
     
         7 . The transistor of  claim 6 , wherein the first epitaxial overlayer is un-doped. 
     
     
         8 . The transistor of  claim 1 , further comprising a first channel isolation structure and a second channel isolation structure disposed on opposite sides of the nonplanar substrate structure, wherein the plurality of trenches comprises a first trench and a second trench, wherein the first channel isolation structure is disposed in the first trench and the second channel isolation structure is disposed in the second trench, and wherein the epitaxial overlayer extends over a portion of the first channel isolation structure in the first trench and over a portion of the second channel isolation structure in the second trench. 
     
     
         9 . The transistor of  claim 8 , further comprising a third trench formed in the first channel isolation structure and a fourth trench formed in the second channel isolation structure, wherein the gate comprises a first vertical gate portion extending into the third trench and a second vertical gate portion extending into the fourth trench. 
     
     
         10 . The transistor of  claim 9 , wherein the epitaxial overlayer extends into the third trench and on the first channel isolation structure and into the fourth trench and on the second channel isolation structure. 
     
     
         11 . The transistor of  claim 10 , wherein the first channel isolation structure and the second channel isolation structure are shallow trench isolation structures. 
     
     
         12 . The transistor of  claim 1 , wherein the nonplanar substrate structure is a first nonplanar substrate structure and the channel doping layer is a first channel doping layer,
 wherein the plurality of trenches define, in the semiconductor substrate, in the channel width plane of the transistor, a second nonplanar substrate structure comprising a plurality of sidewall portions,   wherein the overlayer material of the epitaxial overlayer is epitaxially grown on the second nonplanar substrate structure and encloses a second channel doping layer comprising a doped portion of the semiconductor substrate formed in the second nonplanar substrate structure.   
     
     
         13 . An image sensor, comprising:
 a photodiode formed in a semiconductor substrate;   a transfer transistor coupled to the photodiode and to a floating diffusion, the transfer transistor being operative to transfer charge carriers from the photodiode to the floating diffusion; and   the transistor of  claim 1 , wherein the transistor is a source follower transistor, and wherein the gate is coupled to the floating diffusion.   
     
     
         14 . A semiconductor device, comprising:
 a semiconductor substrate of a first conductive type having an active region and a transistor region comprising a transistor;   a first channel isolation structure disposed between the active region and the transistor region along a channel length direction of the transistor, and a second channel isolation structure disposed in parallel to the first channel isolation structure and spaced apart from the first channel isolation structure;   wherein the transistor comprises:   a planar gate disposed on a surface of semiconductor substrate and over the first channel isolation structure and the second channel isolation structure;   a first gate electrode extending from the planar gate into the first channel isolation structure;   a second gate electrode extending from the planar gate into the second channel isolation structure;   an isolation layer between the semiconductor substrate and the planar gate, between the first gate electrode, the second gate electrode, and the semiconductor substrate;   a plurality of trenches formed in the semiconductor substrate, the plurality of trenches defining, in the semiconductor substrate, in a channel width plane of the transistor, a nonplanar substrate structure comprising a plurality of sidewall portions and a tip portion disposed between the plurality of sidewall portions   a channel doping layer in the semiconductor substrate adjacent to the planar gate, the first gate electrode, and the second gate electrode, wherein the channel doping layer has a second conductive type opposite to the first conductive type, wherein the channel doping layer is implanted into the plurality of sidewall portions and the tip portion of the nonplanar substrate structure, wherein the channel doping layer is a square wave shape that encloses the tip portion and at least partially encloses the plurality of sidewall portions of the nonplanar substrate structure, wherein the square wave shape of the channel doping layer conforms to the nonplanar substate structure, and wherein a bottom of the square wave shape terminates at a same depth as the isolation layer;   an epitaxial overlayer of the semiconductor substrate enclosing the channel doping layer wherein the epitaxial overlayer extends over a portion of the first channel isolation structure in a first trench and over a portion of the second channel isolation structure in a second trench; and   a source and a drain disposed in the semiconductor substrate along the channel length direction on opposite sides of the planar gate;   wherein the isolation layer and epitaxial overlayer are arranged to physically separate the channel doping layer from the planar gate.   
     
     
         15 . The semiconductor device of  claim 14 , wherein each of the first channel isolation structure and the second channel isolation structure comprise a trench partially filled with a dielectric material, wherein each of the first gate electrode and the second gate electrode is positioned on the dielectric material, wherein the epitaxial overlayer extends into the trench of each of the first channel isolation structure and the second channel isolation structure separating the first gate electrode and the second gate electrode from the channel doping layer. 
     
     
         16 . The semiconductor device of  claim 14 , wherein the active region includes at least a photodiode, a floating diffusion, and a transfer gate coupling the photodiode to the floating diffusion, wherein the transistor is a source follower transistor, wherein the planar gate, the first gate electrode and the second gate electrode are electrically connected to the floating diffusion. 
     
     
         17 . The semiconductor device of  claim 14 , wherein the transfer gate includes at least a vertical transfer gate electrode that extends from the surface into the semiconductor substrate and a second channel doping layer disposed in the semiconductor substrate surrounding the vertical transfer gate electrode; wherein the vertical transfer gate electrode is separated from the second channel doping layer by a second epitaxial overlayer. 
     
     
         18 . The semiconductor device of  claim 17 , wherein the epitaxial overlayer, the second epitaxial overlayer, and the semiconductor substrate are formed of a same material. 
     
     
         19 . The semiconductor device of  claim 14 , wherein the channel doping layer, the first gate electrode, and the second gate electrode extend into the semiconductor substrate to a common depth. 
     
     
         20 . The semiconductor device of  claim 14 , wherein the epitaxial overlayer is a first epitaxial overlayer disposed upon a second epitaxial overlayer, wherein the second epitaxial overlayer is the channel doping layer, wherein the first epitaxial overlayer is a un-doped layer and the second epitaxial overlayer is doped with dopant of the second conductive type. 
     
     
         21 . The semiconductor device of  claim 14 , wherein each of the first gate electrode and the second gate electrode extends a first gate width along a channel width plane of the transistor, wherein the first gate width is less than a width of the planar gate in the channel width plane.