Semiconductor structure and method for manufacturing the same

Abstract

A semiconductor device includes a first channel region disposed in a first device region over a substrate; a first gate dielectric layer disposed over the first channel region; a second gate dielectric layer disposed over the second channel region; and a gate electrode disposed over the first gate dielectric layer. The first gate dielectric layer includes a first dipole dopant and the second gate dielectric layer includes a second dipole dopant embedded therein. A boundary between the first gate dielectric layer and the second gate dielectric layer contains the first dipole dopant and the second dipole dopant.

What is claimed is: 
     
         1 . A method comprising:
 depositing a gate dielectric over a first channel region and a second channel region;   depositing a first dipole metal on the gate dielectric in the first channel region and on the gate dielectric in the second channel region;   forming a mask over the first dipole metal;   removing the mask and the first dipole metal from the second channel region, the mask remaining on the first channel region;   depositing a second dipole metal over the mask in the first channel region and over the gate dielectric in the second channel region;   diffusing a first dipole dopant from the first dipole metal into the gate dielectric over the first channel region, thereby forming a first dipole gate dielectric, and diffusing a second dipole dopant from the second dipole metal into the gate dielectric over the second channel region to form a second dipole gate dielectric;   removing the mask from the first dipole metal; and   depositing a gate electrode surrounding the first dipole gate dielectric and the second dipole gate dielectric.   
     
     
         2 . The method of  claim 1 , wherein a corresponding first gate of the first dipole gate dielectric has a first voltage threshold, wherein a corresponding second gate of the second dipole gate dielectric has a second voltage threshold, wherein the second voltage threshold is different than the first voltage threshold. 
     
     
         3 . The method of  claim 1 , further comprising:
 removing the first dipole metal and the second dipole metal prior to depositing the gate electrode.   
     
     
         4 . The method of  claim 1 , further comprising:
 while diffusing the first dipole dopant into the gate dielectric, altering a thickness of the gate dielectric in the first channel region; and   while diffusing the second dipole dopant into the gate dielectric, altering a thickness of the gate dielectric in the second channel region.   
     
     
         5 . The method of  claim 1 , wherein the first dipole dopant diffuses through a partial thickness of the gate dielectric over the first channel region. 
     
     
         6 . The method of  claim 1 , wherein the first dipole metal and the second dipole metal are each selected from lanthanum oxide, yttrium oxide, scandium oxide, gadolinium oxide, aluminum oxide, titanium oxide, indium oxide, gallium oxide, or zinc oxide. 
     
     
         7 . The method of  claim 1 , further comprising:
 in a boundary area at an interface of the first dipole metal and the second dipole metal, diffusing the first dipole dopant and the second dipole dopant into the gate dielectric.   
     
     
         8 . The method of  claim 7 , wherein the boundary area is less than 1 nm wide. 
     
     
         9 . The method of  claim 1 , further comprising:
 diffusing the second dipole dopant into the mask over the first channel region, wherein a depth of diffusion of the second dipole dopant into the mask is less than a thickness of the mask.   
     
     
         10 . A method comprising:
 removing a dummy gate electrode and a dummy gate dielectric to form a first recess in a gate structure, the removing exposing a first transistor channel in a first region of the gate structure and a second transistor channel in a second region of the gate structure;   depositing a gate dielectric over the first transistor channel and the second transistor channel, the gate dielectric lining the first recess;   depositing a first dipole material over the gate dielectric;   forming a masking structure over the first dipole material;   patterning the masking structure to expose a second portion of the first dipole material in the second region, while a first portion of the first dipole material in the first region remains covered by the masking structure;   removing the second portion of the first dipole material;   depositing a second dipole material over the masking structure in the first region and over the gate dielectric in the second region;   annealing the first dipole material and the second dipole material, the annealing driving in a first dipole dopant into the gate dielectric in the first region and driving in a second dipole dopant into the gate dielectric in the second region;   removing the first dipole material, the second dipole material, and the masking structure to expose the gate dielectric; and   forming a gate electrode in the first recess.   
     
     
         11 . The method of  claim 10 , wherein the first dipole material interfaces the second dipole material at an interface of the first region and the second region, further comprising driving in the second dipole dopant into a first boundary region of the first region and driving in the first dipole dopant into a second boundary region of the second region. 
     
     
         12 . The method of  claim 11 , wherein a width of the first boundary region and a width of the second boundary region are less than about 1 nm together. 
     
     
         13 . The method of  claim 10 , wherein a drive-in depth of the first dipole dopant in the first region is different than a drive-in depth of the second dipole dopant in the second region. 
     
     
         14 . The method of  claim 10 , wherein a drive-in depth of the first dipole dopant in the first region is greater than a thickness of the gate dielectric in the first region. 
     
     
         15 . A device comprising:
 a first gate region including a first gate electrode over a first portion of a gate dielectric layer, wherein the first portion of the gate dielectric layer is doped with a first dopant;   a second gate region including a second gate electrode over a second portion of the gate dielectric layer, wherein the second portion of the gate dielectric layer is doped with a second dopant different than the first dopant, wherein a threshold voltage of the first gate region is different than a threshold voltage of the second gate region; and   a boundary region between the first gate region and the second gate region, the boundary region including an overlap between the first portion of the gate dielectric layer doped with the first dopant and the second portion doped with the second dopant, wherein the gate dielectric layer in the boundary region is contiguous with the gate dielectric layer in the first gate region and the gate dielectric layer in the second gate region.   
     
     
         16 . The device of  claim 15 , wherein the boundary region is less than 1 nm wide. 
     
     
         17 . The device of  claim 15 , wherein a distance between the boundary region and a first channel region in the first gate region is less than a distance between the boundary region and a second channel region in the second gate region. 
     
     
         18 . The device of  claim 15 , further comprising:
 an isolation fin disposed between a first channel region in the first gate region and a second channel region in the second gate region, wherein the boundary region is disposed at an upper surface of the isolation fin.   
     
     
         19 . The device of  claim 15 , wherein the gate dielectric layer is a second gate dielectric layer, further comprising a first gate dielectric layer under the second gate dielectric layer, the first dopant extending through the second gate dielectric layer and partially through the first gate dielectric layer. 
     
     
         20 . The device of  claim 19 , wherein a thickness of the first gate dielectric layer in the first gate region is different than a thickness of the first gate dielectric layer in the second gate region.