Receiver and clock and data recovery method thereof

Abstract

A receiver includes an analog to digital converter circuit, a phase detector circuit, a digital loop filter circuit, a phase interpolator circuit, and a bias adaption circuit. The analog to digital converter circuit is configured to convert a first signal into a second signal according to a clock signal. The phase detector circuit is configured to detect a phase of the second signal to generate a phase detection signal. The digital loop filter circuit is configured to scale the phase detection signal with a proportional path gain coefficient and a bias value to generate a third signal. The phase interpolator circuit is configured to generate the clock signal according to the third signal. The bias adaptation circuit is configured to accumulate the phase detection signal to generate the bias value.

What is claimed is: 
     
         1 . A receiver, comprising:
 an analog to digital converter circuit configured to convert a first signal into a second signal according to a clock signal;   a phase detector circuit configured to detect a phase of the second signal to generate a phase detection signal;   a digital loop filter circuit configured to scale the phase detection signal with a proportional path gain coefficient and a bias value to generate a third signal;   a phase interpolator circuit configured to generate the clock signal according to the third signal; and   a bias adaptation circuit configured to accumulate the phase detection signal to generate the bias value.   
     
     
         2 . The receiver of  claim 1 , wherein the digital loop filter circuit is a first-order loop filter circuit. 
     
     
         3 . The receiver of  claim 1 , wherein the digital loop filter circuit generates the third signal without employing an integral path. 
     
     
         4 . The receiver of  claim 1 , wherein the digital loop filter circuit comprises a proportional path, and the bias value is to adjust an input or an output of the proportional path. 
     
     
         5 . The receiver of  claim 1 , wherein the digital loop filter circuit comprises:
 an adder circuit configured to add the bias value and the phase detection signal to generate a fourth signal; and   a multiplier circuit configured to multiply the fourth signal with the proportional path gain coefficient to generate the third signal.   
     
     
         6 . The receiver of  claim 1 , wherein the digital loop filter circuit comprises:
 a multiplier circuit configured to multiply the phase detection signal with the proportional path gain coefficient to generate a fourth signal; and   an adder circuit configured to add the bias value and the fourth signal to generate the third signal.   
     
     
         7 . The receiver of  claim 1 , wherein the bias adaptation circuit comprises:
 a first multiplier circuit configured to multiply the phase detection signal with a first step size value to generate a fifth signal;   a first adder circuit configured to add the fifth signal and a sixth signal to generate a seventh signal;   an averaging circuit configured to accumulate the seventh signal for a predetermined interval and average the accumulated seventh signal to generate an averaging signal;   a second multiplier circuit configured to multiply the averaging signal with a second step size value to generate the sixth signal, wherein the second step size value is higher than the first step size value;   a second adder circuit configured to add the averaging signal and the bias value to update the bias value; and   a register circuit configured to store the bias value.   
     
     
         8 . The receiver of  claim 7 , wherein the bias adaptation circuit further comprises:
 a switch circuit configured to be selectively turned on according to a control signal to transmit the averaging signal to the second adder circuit; and   an adaptive control circuit configured to output the control signal and a reset signal when the predetermined interval is expired,   wherein the averaging circuit is further configured to clear the averaging signal according to the reset signal.   
     
     
         9 . The receiver of  claim 8 , wherein the adaptive control circuit is configured to set the first step size value to be a first value and set the predetermined interval to be a first interval in an initial process of determining the averaging signal, and set the first step size value to be a second value and set the predetermined interval to be a second interval after the initial process is completed, the first value is smaller than the second value, and a duration of the second interval is longer than a duration of the first interval. 
     
     
         10 . The receiver of  claim 7 , wherein the bias adaptation circuit further comprises:
 a third multiplier circuit configured to multiply the phase detection signal with the proportional path gain coefficient to generate an eighth signal,   wherein the first multiplier circuit is configured to multiply the eighth signal with the first step size value to generate the fifth signal.   
     
     
         11 . The receiver of  claim 7 , wherein the second step size value is a difference between a value of 1 and the first step size value. 
     
     
         12 . A clock and data recovery method, comprising:
 converting a first signal into a second signal according to a clock signal;   generating a phase detection signal according to a phase of the second signal;   scaling the phase detection signal with a proportional path gain coefficient and a bias value to generate a third signal;   generating the clock signal according to the third signal; and   accumulating the phase detection signal to generate the bias value.   
     
     
         13 . The clock and data recovery method of  claim 12 , wherein the phase detection signal is scaled by a digital loop filter circuit, and the digital loop filter circuit is a first-order loop circuit. 
     
     
         14 . The clock and data recovery method of  claim 12 , wherein the phase detection signal is scaled by a digital loop filter circuit, and the digital loop filter circuit generates the third signal without employing an integral path. 
     
     
         15 . The clock and data recovery method of  claim 12 , wherein the phase detection signal is scaled by a digital loop filter circuit, the digital loop filter circuit comprises a proportional path, and the bias value is to adjust an input or an output of the proportional path. 
     
     
         16 . The clock and data recovery method of  claim 12 , wherein scaling the phase detection signal with the proportional path gain coefficient and the bias value to generate the third signal comprises:
 adding the bias value and the phase detection signal to generate a fourth signal; and   multiplying the fourth signal with the proportional path gain coefficient to generate the third signal.   
     
     
         17 . The clock and data recovery method of  claim 12 , wherein scaling the phase detection signal with the proportional path gain coefficient and the bias value to generate the third signal comprises:
 multiplying the phase detection signal with the proportional path gain coefficient to generate a fourth signal; and   adding the bias value and the fourth signal to generate the third signal.   
     
     
         18 . The clock and data recovery method of  claim 12 , wherein accumulating the phase detection signal to generate the bias value comprises:
 multiplying the phase detection signal with a first step size value to generate a fifth signal;   adding the fifth signal and a sixth signal to generate a seventh signal;   accumulating the seventh signal for a predetermined interval and averaging the accumulated seventh signal to generate an averaging signal;   multiplying the averaging signal with a second step size value to generate the sixth signal, wherein the second step size value is higher than the first step size value;   adding the averaging signal and the bias value to update the bias value; and   storing the bias value.   
     
     
         19 . The clock and data recovery method of  claim 18 , wherein accumulating the phase detection signal to generate the bias value further comprises:
 selectively turned on a switch according to a control signal to transmit the averaging signal to an adder circuit, wherein the adder circuit is configured to add the averaging signal and the bias value to update the bias value;   outputting the control signal and a reset signal when the predetermined interval is expired; and   clearing the averaging signal according to the reset signal.   
     
     
         20 . The clock and data recovery method of  claim 18 , further comprising:
 setting the first step size value to be a first value and setting the predetermined interval to be a first interval in an initial process of determining the averaging signal; and   setting the first step size value to be a second value and setting the predetermined interval to be a second interval after the initial process is completed,   wherein the first value is smaller than the second value, and a duration of the second interval is longer than a duration of the first interval.