Semiconductor structure and its fabrication method, memory and memory system

Abstract

A fabrication method of a semiconductor structure includes forming a stack structure and a memory channel structure on a substrate. The memory channel structure penetrates through the stack structure along a stack direction and extends into the substrate to form an extension part. The memory channel structure includes a memory function layer and a channel layer. The method further includes removing the substrate and exposing the extension part, and forming a sacrificial layer on a side of the stack structure where the substrate is removed from. The sacrificial layer wraps a part of the exposed extension part. The method also includes removing the memory function layer in the unwrapped extension part and exposing the corresponding channel layer, removing the sacrificial layer, exposing the remaining memory function layer in the extension part, and forming a semiconductor layer on a side of the stack structure where the sacrificial layer is removed from.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a stack structure including a gate structure and a gate spacer layer arranged alternately;   a memory channel structure penetrating through the stack structure along a stack direction and protruding out of the stack structure to form an extension part, the memory channel structure including a memory function layer and a channel layer; and   a semiconductor layer which is on a side of the stack structure close to the extension part and wraps an end face of the extension part, and a side of the memory function layer and a side of the channel layer in the extension part.   
     
     
         2 . The semiconductor structure according to  claim 1 , wherein the channel layer in the extension part has a first extension height along the stack direction, the memory function layer in the extension part has a second extension height along the stack direction, and the first extension height is greater than the second extension height. 
     
     
         3 . The semiconductor structure according to  claim 1 , further comprising:
 an insulating layer on a side of the semiconductor layer away from the stack structure;   a source contact in the insulating layer and connected with the semiconductor layer, the source contact being electrically connected with an external circuit.   
     
     
         4 . A memory system, comprising at least one memory and a controller coupled with the memory, wherein the controller is used to control the memory to store data,
 the at least one memory includes a semiconducter structure and a peripheral circuit structure, the semiconducter structure including a stack structure, a memory channel structure, and a semiconductor layer,   the stack structure includes a gate structure and a gate spacer layer arranged alternately,   the memory channel structure penetrates through the stack structure along a stack direction and protrudes out of the stack structure to form an extension part, the memory channel structure including a memory function layer and a channel layer,   the semiconductor layer is on a side of the stack structure close to the extension part and wraps an end face of the extension part, and a side of the memory function layer and a side of the channel layer in the extension part, and   the peripheral circuit structure is bonded with the stack structure on a side of the stack structure away from the semiconductor layer, so that the peripheral circuit structure is electrically connected with the semiconductor structure.