Memory system and method for controlling nonvolatile memory

Abstract

According to one embodiment, a memory system receives, from a host, a write request including a first identifier associated with one write destination block and storage location information indicating a location in a write buffer on a memory of the host in which first data to be written is stored. When the first data is to be written to a nonvolatile memory, the memory system obtains the first data from the write buffer by transmitting a transfer request including the storage location information to the host, transfers the first data to the nonvolatile memory, and writes the first data to the one write destination block.

What is claimed is: 
     
         1 . A memory system connectable to a host, comprising:
 a nonvolatile memory; and   a controller electrically connected to the nonvolatile memory and configured to:   receive, from the host, a first write request that includes storage location information indicating a first location of a write buffer on a memory of the host as a transfer source of first data;   at a first timing, transfer the first data from the first location of the write buffer of the host to the nonvolatile memory by transmitting, to the host, a transfer request that includes information indicating the first location of the write buffer of the host; and   at a fifth timing after the first timing, without receiving the first write request again, transfer the first data again from the first location of the write buffer of the host to the nonvolatile memory by transmitting, to the host again, the transfer request that includes the information indicating the first location of the write buffer of the host.   
     
     
         2 . The memory system of  claim 1 , wherein
 the first data is written to the nonvolatile memory using a multi-step program operation that includes at least a first-step program operation and a second-step program operation, and the controller is further configured to:   at a second timing after the first timing and before the fifth timing, instruct the nonvolatile memory to perform the first-step program operation for the first data; and   at a sixth timing after the fifth timing, instruct the nonvolatile memory to perform the second-step program operation for the first data.   
     
     
         3 . The memory system of  claim 2 , wherein
 the nonvolatile memory includes a page buffer and a plurality of word lines each connecting a plurality of memory cells, the plurality of word lines including at least a first word line, and   the controller is configured to:   
       at the first timing, transfer the first data from the first location of the write buffer of the host to the page buffer;
 at the second timing, instruct the nonvolatile memory to perform the first-step program operation for the first data on the plurality of memory cells connected to the first word line; 
 at the fifth timing, transfer the first data from the first location of the write buffer of the host to the page buffer again; and 
 at the sixth timing, instruct the nonvolatile memory to perform the second-step program operation for the first data on the plurality of memory cells connected to the first word line. 
 
     
     
         4 . The memory system of  claim 3 , wherein
 the plurality of word lines further includes a second word line, and   the controller is further configured to:   at a third timing after the second timing and before the fifth timing, transfer second data from the write buffer of the host to the page buffer; and   at a fourth timing after the third timing and before the fifth timing, instruct the nonvolatile memory to perform the first-step program operation for the second data on the plurality of memory cells connected to the second word line.   
     
     
         5 . The memory system of  claim 1 , further comprising:
 an internal buffer, wherein   the controller is configured to:   at the first timing, store in the internal buffer, the first data transferred from the write buffer of the host, and then transfer the first data from the internal buffer to the nonvolatile memory; and   at the fifth timing, store in the internal buffer, the first data transferred again from the write buffer of the host, and then transfer the first data from the internal buffer to the nonvolatile memory again.   
     
     
         6 . The memory system of  claim 1 , wherein
 the nonvolatile memory includes a plurality of physical blocks,   the controller is further configured to:
 manage a plurality of block groups, each of the plurality of block groups including at least one of the plurality of physical blocks; and 
 perform a data erase operation in a unit of the block group, the first write request includes at least a first identifier to identify each of the plurality of block groups, and 
   the controller is further configured to determine, based on the first identifier included in the first write request, a write-destination block group from the plurality of block groups to write the first data.   
     
     
         7 . The memory system of  claim 6 , wherein
 the nonvolatile memory further includes a plurality of chips,   the first write request further includes a second identifier to identify each of the plurality of chips, and   the controller is configured to determine, further based on the second identifier included in the first write request, the write-destination block group from the plurality of block groups.   
     
     
         8 . The memory system of  claim 6 , wherein
 each of the plurality of block groups includes only one physical block.   
     
     
         9 . The memory system of  claim 1 , wherein
 the nonvolatile memory includes a plurality of blocks, each of the plurality of blocks being a unit for a data erase operation,   the controller is further configured to:
 manage a plurality of streams; and 
 assign the plurality of streams to the plurality of blocks, 
   the first write request includes at least a first identifier to identify each of the plurality of streams, and   the controller is further configured to determine, based on the first identifier included in the first write request, a write-destination block from the plurality of blocks to write the first data.   
     
     
         10 . The memory system of  claim 1 , wherein
 the controller is further configured to:
 in response to receiving, from the host, a read request to read the first data in a period after starting to transfer the first data to the nonvolatile memory before the first data becomes readable from the nonvolatile memory, 
 transmit, to the host as a response to the read request, a request that the host obtain the first data from the write buffer of the host. 
   
     
     
         11 . A memory system connectable to a host, comprising:
 a nonvolatile memory; and   a controller electrically connected to the nonvolatile memory and configured to:
 receive, from the host, a first write request that includes storage location information indicating a first location of a write buffer on a memory of the host as a transfer source of first data; and 
 write the first data to the nonvolatile memory using a multi-step program operation that includes a plurality of program operations by: 
 in each of the plurality of program operations of the multi-step program operation, 
 without receiving the first write request again, obtaining the first data from the first location of the write buffer of the host by transmitting, to the host, a transfer request that includes information indicating the first location of the write buffer of the host; and 
 transferring the first data to the nonvolatile memory. 
   
     
     
         12 . The memory system of  claim 11 , wherein
 the controller is further configured to:   in each of the plurality of program operations of the multi-step program operation,   after transferring the first data to the nonvolatile memory, instruct the nonvolatile memory to perform one of the plurality of program operations for the first data.   
     
     
         13 . The memory system of  claim 12 , wherein
 the nonvolatile memory includes a page buffer and a plurality of word lines each connecting a plurality of memory cells, the plurality of word lines including at least a first word line, and   the controller is configured to:
 in each of the plurality of program operations of the multi-step program operation, 
 transfer the first data from the first location of the write buffer of the host to the page buffer; and 
   instruct the nonvolatile memory to perform the one of the plurality of program operations for the first data on the plurality of memory cells connected to the first word line.   
     
     
         14 . The memory system of  claim 13 , wherein
 the plurality of program operations includes at least a first-step program operation and a second-step program operation,   the plurality of word lines further includs-includes a second word line, and   the controller is further configured to:
 after instructing the nonvolatile memory to perform the first-step program operation for the first data on the plurality of memory cells connected to the first word line and before transferring the first data from the first location of the write buffer of the host to the page buffer for the second-step program operation of the first data, 
 transfer second data from the write buffer of the host to the page buffer; and 
 instruct the nonvolatile memory to perform the first-step program operation for the second data on the plurality of memory cells connected to the second word line. 
   
     
     
         15 . The memory system of  claim 11 , further comprising:
 an internal buffer, wherein   the controller is configured to:
 in each of the plurality of program operations of the multi-step program operation, 
 store in the internal buffer, the first data transferred from the write buffer of the host, and then transfer the first data from the internal buffer to the nonvolatile memory. 
   
     
     
         16 . The memory system of  claim 11 , wherein
 the nonvolatile memory includes a plurality of physical blocks,   the controller is further configured to:
 manage a plurality of block groups, each of the plurality of block groups including at least one of the plurality of physical blocks; and 
 perform a data erase operation in a unit of the block group, 
   the first write request includes at least a first identifier to identify each of the plurality of block groups, and   the controller is further configured to determine, based on the first identifier included in the first write request, a write-destination block group from the plurality of block groups to write the first data.   
     
     
         17 . The memory system of  claim 16 , wherein
 the nonvolatile memory further includes a plurality of chips,   the first write request further includes a second identifier to identify each of the plurality of chips, and   the controller is configured to determine, further based on the second identifier included in the first write request, the write-destination block group from the plurality of block groups.   
     
     
         18 . The memory system of  claim 16 , wherein
 each of the plurality of block groups includes only one physical block.   
     
     
         19 . The memory system of  claim 11 , wherein
 the nonvolatile memory includes a plurality of blocks, each of the plurality of blocks being a unit for a data erase operation,   the controller is further configured to:
 manage a plurality of streams; and 
 assign the plurality of streams to the plurality of blocks, 
   the first write request includes at least a first identifier to identify each of the plurality of streams, and   the controller is further configured to determine, based on the first identifier included in the first write request, a write-destination block from the plurality of blocks to write the first data.   
     
     
         20 . The memory system of  claim 11 , wherein
 the controller is further configured to:   in response to receiving, from the host, a read request to read the first data in a period after starting to transfer the first data to the nonvolatile memory before the first data becomes readable from the nonvolatile memory,   transmit, to the host as a response to the read request, a request that the host obtain the first data from the write buffer of the host.