Memory systems, systems and operating methods thereof, computer-readable storage mediums

Abstract

The present disclosure provides example memory systems and operating methods thereof, systems and operating methods thereof, and computer-readable storage mediums. An example memory system includes an interface and an interface controller, the interface is connected to a host through a link; the interface controller is configured to: determine whether link equalization is to be redone based on a temperature change of the memory system and error counts of the interface; the error counts include a first error count and a second error count, and the first error count is a number of recoverable errors in data packets received by the interface, and the second error count is a number of times that the interface switches between a normal operating state and a recovery state; in response to the link equalization being to be redone, trigger the link equalization.

What is claimed is: 
     
         1 . A memory system, comprising:
 an interface connected to a host through a link; and   an interface controller, configured to:
 determine whether a link equalization is to be redone based on a temperature change of the memory system and error counts of the interface, wherein the error counts include a first error count and a second error count, the first error count is a number of recoverable errors in data packets received by the interface, and the second error count is a number of times that the interface switches between a normal operating state and a recovery state, and wherein to determine whether the link equalization is to be redone comprises to:
 obtain a current temperature of the memory system and a temperature of the memory system at which the link equalization was performed last time; 
 in response to an absolute value of a difference between the current temperature and the temperature of the memory system at which the link equalization was performed last time being greater than a first preset value, obtain the first error count and the second error count; and 
 in response to the first error count being greater than a second preset value or the second error count being greater than a third preset value, determine that the link equalization is to be redone; and 
 
 in response to a determination the link equalization is to be redone, trigger the link equalization. 
   
     
     
         2 . The memory system of  claim 1 , wherein the interface controller is further configured to:
 in response to a transmission rate of the link being greater than or equal to 8 GT/s, set the first error count and the second error count to zero, and start a timer; and   obtain the current temperature of the memory system each time a timing of the timer reaches a timing period.   
     
     
         3 . The memory system of  claim 1 , wherein the interface controller is further configured to set the first error count and the second error count to zero after the link equalization is successful. 
     
     
         4 . The memory system of  claim 1 , wherein the interface controller is further configured to:
 request a transmission at the interface to be suspended and wait for the interface to enter an idle state before triggering the link equalization; and   set a flag indicating performing the link equalization in a control register of the interface after the interface enters the idle state.   
     
     
         5 . The memory system of  claim 4 , wherein the interface is configured to, in response to the flag indicating performing the link equalization, perform the link equalization, which includes sending a training sequence to the host to notify the host to perform the link equalization. 
     
     
         6 . The memory system of  claim 1 , wherein the memory system further includes a memory device and a memory controller coupled to the memory device and is configured to control the memory device, wherein:
 the memory controller includes the interface and the interface controller, or   the memory controller includes the interface, and the interface controller is external to the memory controller.   
     
     
         7 . The memory system of  claim 1 , wherein the interface includes an interface of high-speed serial computer expansion bus standard. 
     
     
         8 . A computer-readable storage medium, wherein the computer-readable storage medium stores computer program that when executed, may implement a method for operating a memory system, comprising:
 determining whether a link equalization is to be redone based on a temperature change of the memory system and error counts of an interface, wherein the error counts include a first error count and a second error count, the first error count is a number of recoverable errors in data packets received by the interface, and the second error count is a number of times that the interface switches between a normal operating state and a recovery state, and wherein determining whether the link equalization is to be redone comprises:
 obtaining a current temperature of the memory system and a temperature of the memory system at which the link equalization was performed last time; 
 in response to an absolute value of a difference between the current temperature and the temperature of the memory system at which the link equalization was performed last time being greater than a first preset value, obtaining the first error count and the second error count; and 
 in response to the first error count being greater than a second preset value or the second error count being greater than a third preset value, determining that the link equalization is to be redone; and 
   in response to a determination the link equalization is to be redone, triggering the link equalization.   
     
     
         9 . The computer-readable storage medium of  claim 8 , wherein the method for operating the memory system further includes:
 in response to a transmission rate of a link being greater than or equal to 8 GT/s, setting the first error count and the second error count to zero, and starting a timer; and   obtaining the current temperature of the memory system each time a timing of the timer reaches a timing period.   
     
     
         10 . The computer-readable storage medium of  claim 8 , wherein the method for operating the memory system further includes setting the first error count and the second error count to zero after the link equalization is successful. 
     
     
         11 . The computer-readable storage medium of  claim 8 , wherein the method for operating the memory system further includes requesting a transmission at the interface to be suspended and waiting for the interface to enter an idle state before triggering the link equalization, wherein the triggering the link equalization includes setting a flag indicating performing the link equalization in a control register of the interface after the interface enters the idle state. 
     
     
         12 . The computer-readable storage medium of  claim 11 , wherein the method for operating the memory system further includes, in response to the flag indicating performing the link equalization, performing the link equalization, which includes sending a training sequence to a host to notify the host to perform the link equalization. 
     
     
         13 . The computer-readable storage medium of  claim 8 , wherein the interface includes an interface of high-speed computer expansion bus standard. 
     
     
         14 . The computer-readable storage medium of  claim 8 , wherein the memory system further includes a memory device and a memory controller coupled to the memory device and is configured to control the memory device, wherein:
 the memory controller includes the interface and an interface controller, or   the memory controller includes the interface, and the interface controller is external to the memory controller.   
     
     
         15 . A method of operating a memory system, comprising:
 determining whether a link equalization is to be redone based on a temperature change of the memory system and error counts of an interface, wherein the error counts include a first error count and a second error count, the first error count is a number of recoverable errors in data packets received by the interface, and the second error count is a number of times that the interface switches between a normal operating state and a recovery state, and wherein determining whether the link equalization is to be redone comprises:
 obtaining a current temperature of the memory system and a temperature of the memory system at which the link equalization was performed last time; 
 in response to an absolute value of a difference between the current temperature and the temperature of the memory system at which the link equalization was performed last time being greater than a first preset value, obtaining the first error count and the second error count; and 
 in response to the first error count being greater than a second preset value or the second error count being greater than a third preset value, determining that the link equalization is to be redone; and 
   in response to a determination the link equalization is to be redone, triggering the link equalization.   
     
     
         16 . The method of  claim 15 , further including:
 in response to a transmission rate of a link being greater than or equal to 8 GT/s, setting the first error count and the second error count to zero, and starting a timer; and   obtaining the current temperature of the memory system each time a timing of the timer reaches a timing period.   
     
     
         17 . The method of  claim 15 , further including setting the first error count and the second error count to zero after the link equalization is successful. 
     
     
         18 . The method of  claim 15 , further including requesting a transmission at the interface to be suspended and waiting for the interface to enter an idle state before triggering the link equalization, wherein the triggering the link equalization includes setting a flag indicating performing the link equalization in a control register of the interface after the interface enters the idle state. 
     
     
         19 . The method of  claim 18 , further including, in response to the flag indicating performing the link equalization, performing the link equalization, which includes sending a training sequence to a host to notify the host to perform the link equalization. 
     
     
         20 . The method of  claim 15 , wherein the interface includes an interface of high-speed computer expansion bus standard.