Thermal mitigation systems and methods for multi-core processors

Abstract

A system for performing thermal mitigation in a multi-core processor determines which processing core(s) of the processor is responsible for causing the temperature to rise to an undesired level and then performs one or more thermal mitigation steps only in the responsible core to avoid degrading performance of the other cores. The system monitors digital activity (DA) of the pipeline stages of the cores, determines when the DA of a processing stage has caused temperature to rise to a particular level and then reduces the DA of at least one processing stage of the responsible core in order to reduce temperature. The system can also take one or more other thermal mitigation steps based on monitored temperature values, such as reducing clock frequency or selecting a different V/F corner of the responsible core.

What is claimed is: 
     
         1 . A method for performing thermal mitigation in a multi-core processor, comprising:
 with at least first and second digital activity (DA) sensors disposed in first and second processing cores, respectively, of the multi-core processor, producing first and second sets of DA values, respectively;   with first and second temperature sensors disposed in the first and second processing cores, respectively, of the multi-core processor, producing first and second sets of temperature values, respectively;   in a processing circuit, receiving the first and second sets of temperature values and processing the first and second sets of temperature values to determine whether one or more thermal mitigation steps need to be performed in at least one of the first processing core and the second processing core;   comparing each temperature value to a first-order temperature threshold (TH) value to determine whether any of the temperature values exceeds the first-order temperature TH value;   reducing a clock frequency of the first processing core in response to at least one of the temperature values of the first set of temperature values exceeds the first-order temperature TH value, and reducing a clock frequency of the second processing core in response to at least one of the temperature values of the second set of temperature values exceeds the first-order temperature TH value;   in the processing circuit, receiving the first and second sets of DA values;   in the processing circuit, aggregating the DA values and determining first and second maximum DA values of the first and second sets of DA values, respectively;   in the processing circuit, processing the first and second sets of DA values to determine whether at least one of the DA values exceeds a DA threshold (TH) value, wherein if a determination is made that at least one of the DA values exceeds the DA TH value, reducing the digital activity of at least one processing stage of one of the first and second processing cores that is associated with the DA value that exceeded the DA TH value;   in the processing circuit, prior to processing the first and second sets of DA values to determine whether at least one of the DA values exceeds the DA TH value: if a determination is made that a temperature value compared to the first-order temperature TH value does not exceed the first-order temperature TH value, comparing the temperature value that did not exceed the first-order temperature TH value to a second-order temperature TH value that is less than the first-order temperature TH value;   if the temperature value compared to the second-order temperature TH value is of the first set of temperature values and exceeds the second-order temperature TH value, comparing the first maximum DA value to the DA TH value; and   if a determination is made that the first maximum DA value exceeds the DA TH value, reducing a digital activity of at least a first processing stage of the first processing core.   
     
     
         2 . The method of  claim 1 , wherein the processing of the first and second sets of DA values to determine whether at least one of the DA values exceeds the DA TH value comprises:
 if the temperature value compared to the second-order temperature TH value is of the second set of temperature values and exceeds the second-order temperature TH value, comparing the second maximum DA value to the DA TH value; and   if a determination is made that the second maximum DA value exceeds the DA TH value, reducing the digital activity of at least a second processing stage of the second processing core.   
     
     
         3 . The method of  claim 2 , wherein the first processing stage of the first processing core is an execution unit (EU) processing stage, and wherein the digital activity of the EU processing stage is reduced by reducing a number of instructions per cycle (IPCs) that are executed by the EU processing stage. 
     
     
         4 . The method of  claim 2 , wherein the second processing stage of the second processing core is an execution unit (EU) processing stage, and wherein the digital activity of the EU processing stage is reduced by reducing a number of instructions per cycle (IPCs) that are executed by EU processing stage. 
     
     
         5 . The method of  claim 2 , further comprising:
 if it is determined that the first maximum DA value does not exceed the DA TH value, reducing a supply voltage/clock frequency (V/F) corner used by the first processing core.   
     
     
         6 . The method of  claim 5 , further comprising:
 if it is determined that the second maximum DA value does not exceed the DA TH value, reducing a supply voltage/clock frequency (V/F) corner used by the second processing core.   
     
     
         7 . The method of  claim 1 , wherein the multi-core processor is a multi-core processor of a system-on-a-chip (SoC) integrated circuit (IC) package of a portable computing device (PCD). 
     
     
         8 . A system for performing thermal mitigation in a multi-core processor, comprising:
 first and second digital activity (DA) sensors disposed in first and second processing cores, respectively, of the multi-core processor, configured to produce first and second sets of DA values, respectively;   first and second temperature sensors disposed in the first and second processing cores, respectively, of the multi-core processor, configured to produce first and second sets of temperature values, respectively;   a processing circuit configured to receive the first and second sets of temperature values and configured to process the first and second sets of temperature values to determine whether one or more thermal mitigation steps need to be performed in at least one of the first processing core and the second processing core;   the processing circuit configured to compare each temperature value to a first-order temperature threshold (TH) value to determine whether any of the temperature values exceeds the first-order temperature TH value;   the processing circuit reducing a clock frequency of the first processing core in response to at least one of the temperature values of the first set of temperature values exceeds the first-order temperature TH value, and the processing circuit reducing a clock frequency of the second processing core in response to at least one of the temperature values of the second set of temperature values exceeds the first-order temperature TH value;   the processing circuit configured to receive the first and second sets of DA values;   the processing circuit aggregating the DA values and determining first and second maximum DA values of the first and second sets of DA values, respectively; and   the processing circuit processing the first and second sets of DA values to determine whether at least one of the DA values exceeds a DA threshold (TH) value, wherein if a determination is made by the processing circuit that at least one of the DA values exceeds the DA TH value, the processing circuit is configured to reduce the digital activity of at least one processing stage of at least one of the first and second processing cores that is associated with the DA value that exceeded the DA TH value;   the processing circuit prior to processing the first and second sets of DA values to determine whether at least one of the DA values exceeds a DA TH value:
 if a determination is made that a temperature value compared to the first-order temperature TH value does not exceed the first-order temperature TH value, comparing the temperature value that did not exceed the first-order temperature TH value to a second-order temperature TH value that is less than the first-order temperature TH value; 
 if the temperature value compared to the second-order temperature TH value is of the first set of temperature values and exceeds the second-order temperature TH value, comparing the first maximum DA value to the DA TH value; and 
 if a determination is made that the first maximum DA value exceeds the DA TH value, reducing a digital activity of at least a first processing stage of the first processing core. 
   
     
     
         9 . The system of  claim 8 , wherein the processing circuit is further configured to perform the processing of the first and second sets of DA values to determine whether at least one of the DA values exceeds a DA TH value by:
 determining if the temperature value compared to the second-order temperature TH value is of the second set of temperature values and exceeds the second-order temperature TH value, comparing the second maximum DA value to the DA TH value; and   if a determination is made that the second maximum DA value exceeds the DA TH value, reducing the digital activity of at least a second processing stage of the second processing core.   
     
     
         10 . The system of  claim 9 , wherein the first processing stage of the first processing core is an execution unit (EU) processing stage, and wherein the digital activity of the EU processing stage is reduced by reducing a number of instructions per cycle (IPCs) that are executed by the EU processing stage. 
     
     
         11 . The system of  claim 9 , wherein the second processing stage of the second processing core is an execution unit (EU) processing stage, and wherein the digital activity of the EU processing stage is reduced by reducing a number of instructions per cycle (IPCs) that are executed by EU processing stage. 
     
     
         12 . The system of  claim 9 , wherein the processing circuit is further configured to:
 reduce a supply voltage/clock frequency (V/F) corner used by the first processing core if it is determined that the first maximum DA value does not exceed the DA TH value.   
     
     
         13 . The system of  claim 12 , wherein the processing circuit is further configured to:
 reduce a supply voltage/clock frequency (V/F) corner used by the second processing core if it is determined that the second maximum DA value does not exceed the DA TH value.   
     
     
         14 . The system of  claim 8 , wherein the multi-core processor is a multi-core processor of a system-on-a-chip (SoC) integrated circuit (IC) package of a portable computing device (PCD). 
     
     
         15 . A non-transitory computer-readable medium comprising computer instructions for execution by a processing circuit of a multi-core processor for performing thermal mitigation in the multi-core processor, the computer instructions comprising:
 a first set of computer instructions for receiving at least first and second sets of digital activity (DA) values produced by first and second DA sensors disposed in first and second processing cores, respectively, of the multi-core processor;   a second set of computer instructions for receiving first and second sets of temperature values produced by first and second temperature sensors, respectively, disposed in the first and second processing cores, respectively, of the multi-core processor;   a third set of computer instructions for processing the first and second sets of temperature values to determine whether one or more thermal mitigation steps need to be performed in at least one of the first processing core and the second processing core;   a fourth set of computer instructions for comparing each temperature value to a first-order temperature threshold (TH) value to determine whether any of the temperature values exceeds the first-order temperature TH value;   a fifth set of computer instructions for reducing a clock frequency of the first processing core in response to at least one of the temperature values of the first set of temperature values exceeds the first-order temperature TH value;   a sixth set of computer instructions for reducing a clock frequency of the second processing core in response to at least one of the temperature values of the second set of temperature values exceeds the first-order temperature TH value;   a seventh set of computer instructions for aggregating the DA values and determining first and second maximum DA values of the first and second sets of DA values, respectively;   an eighth set of instructions for processing the first and second sets of DA values to determine whether at least one of the DA values exceeds a DA threshold (TH) value; and   a ninth set of computer instructions for execution by the processing circuit if a determination is made that at least one of the DA values exceeds the DA TH value, wherein execution by the third set of instructions reduces the digital activity of at least one processing stage of at least one of the first and second processing cores, said at least one processing stage being associated with said at least one of the DA values that exceeded the DA TH value;   a tenth set of computer instructions for comparing a temperature value that did not exceed the first-order temperature TH value to a second-order temperature TH value that is less than the first-order temperature TH value;   an eleventh set of computer instructions for comparing the first maximum DA value to the DA TH value if the temperature value compared to the second-order temperature TH value is of the first set of temperature values and exceeds the second-order temperature TH value; and   a twelfth set of computer instructions for reducing a digital activity of at least a first processing stage of the first processing core if a determination is made that the first maximum DA value exceeds the DA TH value.   
     
     
         16 . The computer-readable medium of  claim 15 , wherein the twelfth set of computer instructions further comprises:
 computer instructions comparing the second maximum DA value to the DA TH value if the temperature value compared to the second-order temperature TH value is of the second set of temperature values and exceeds the second-order temperature TH value; and   computer instructions for reducing the digital activity of at least a second processing stage of the second processing core if a determination is made that the second maximum DA value exceeds the DA TH value.