Pipelined successive approximation register analog-to-digital converter, integrated circuit, and electronic device

Abstract

Disclosed are a pipelined successive approximation register analog-to-digital converter, an integrated circuit, and an electronic device. The pipelined successive approximation register analog-to-digital converter includes: a first-stage successive approximation register analog-to-digital converter (10), a residue amplifier (30), a second-stage successive approximation register analog-to-digital converter (20), and a digital coding unit (40).

What is claimed is: 
     
         1 . A pipelined successive approximation register analog-to-digital converter, comprising:
 a first-stage successive approximation register analog-to-digital converter, including a first digital-to-analog converter, a first comparator and a first digital control logic unit sequentially connected, wherein the first digital-to-analog converter includes a first capacitor array having one first complement bit capacitor and M bit first capacitors, a first end of the first complement bit capacitor and a first end of each of the first capacitors are respectively connected to an analog input voltage, a second end of each of the first capacitors is connected to a positive going reference voltage or a negative going reference voltage through a multi-way selection switch, and a second end of the first complement bit capacitor is connected to a negative going reference voltage; a capacitance value of the first complement bit capacitor is equal to a capacitance value of a first bit capacitor in the M bit first capacitors, and capacitance values of the M bit first capacitors are sequentially increased by a power of 2 from small to large according to the number of bits, where M is an integer larger than 1;   a residue amplifier having an input end connected to a residual voltage output from the first digital-to-analog converter;   a second-stage successive approximation register analog-to-digital converter, including a second digital-to-analog converter, a second comparator and a second digital control logic unit sequentially connected, wherein the second digital-to-analog converter includes a second capacitor array having one gain halving capacitor, one second complement bit capacitor, and N−1 bit second capacitors, a first end of the gain halving capacitor, a first end of the second complement bit capacitor, and a first end of each of the second capacitors are respectively connected to an output end of the residue amplifier, a second end of each of the second capacitors is connected to a positive going reference voltage or a negative going reference voltage through a multi-way selection switch, and a second end of the gain halving capacitor, and a second end of the second complement bit capacitor are respectively connected to a negative going reference voltage, a capacitance value of the second complement bit capacitor is equal to a capacitance value of a first bit capacitor in the N−1 bit second capacitors, capacitance values of the N−1 bit second capacitors are sequentially increased by a power of 2 from small to large according to the number of bits, and a capacitance value of the gain halving capacitor is a sum of the capacitance values of the N−1 bit second capacitors and the second complement bit capacitor, where N is an integer greater than 1; and   a digital coding unit connected to output ends of the first digital control logic unit and the second digital control logic unit.   
     
     
         2 . The pipelined successive approximation register analog-to-digital converter according to  claim 1 , wherein the analog input voltage is a differential voltage; and two first capacitor arrays are provided and correspondingly connected to a positive going input voltage and a negative going input voltage in the differential voltage. 
     
     
         3 . The pipelined successive approximation register analog-to-digital converter according to  claim 2 , wherein the residue amplifier is a differential amplifier having two input ends correspondingly connected to residual voltages output from the two first capacitor arrays. 
     
     
         4 . The pipelined successive approximation register analog-to-digital converter according to  claim 3 , wherein the differential amplifier has two output ends; and two second capacitor arrays are provided and correspondingly connected to the two output ends of the differential amplifier. 
     
     
         5 . The pipelined successive approximation register analog-to-digital converter according to  claim 1 , wherein the residue amplifier has an amplification factor being an (M−2) th  power of 2. 
     
     
         6 . The pipelined successive approximation register analog-to-digital converter according to  claim 1 , wherein the second end of each first capacitor is further connected to a common mode voltage through the multi-way selection switch. 
     
     
         7 . The pipelined successive approximation register analog-to-digital converter according to  claim 1 , wherein the second end of each second capacitor is further connected to a common mode voltage through the multi-way selection switch. 
     
     
         8 . The pipelined successive approximation register analog-to-digital converter according to  claim 1 , further comprising a sample and hold circuit connected to the analog input voltage and the first digital-to-analog converter. 
     
     
         9 . An integrated circuit; comprising a pipelined successive approximation register analog-to-digital converter the pipelined successive approximation register analog-to-digital converter comprising:
 a first-stage successive approximation register analog-to-digital converter, including a first digital-to-analog converter, a first comparator and a first digital control logic unit sequentially connected, wherein the first digital-to-analog converter includes a first capacitor array having one first complement bit capacity and M bit first capacitors, a first end of the first complement bit capacitor and a first end of each of the first capacitors are respectively connected to an analog input voltage, a second end of the each of the first capacitors is connected to a positive going reference voltage or a negative going reference voltage through a multi-way selection switch, and a second end of the first complement bit capacitor is connected to a negative going reference voltage; a capacitance value of the first complement bit capacitor is equal to a capacitance value of a first bit capacitor in the M bit first capacitors, and capacitance values of the M bit first capacitors are sequentially increased by a power of 2 from small to large according to the number of bits, where M is an integer larger than 1,   a residue amplifier having an input end connected to a residual voltage output from the first digital-to-analog converter;   a second-stage successive approximation register analog-to-digital converter, including a second digital-to-analog converter, a second comparator and a second digital control logic unit sequentially connected, wherein the second digital-to-analog converter includes a second capacitor array having one gain halving capacitor, one second complement bit capacitor, and N−1 bit second capacitors, a first end of the gain halving capacitor, a first end of the second complement bit capacitor, and a first end of each of the second capacitors are respectively connected to an output end of the residue amplifier, a second end of each of the second capacitors is connected to a positive going reference voltage of a negative going reference voltage through a multi-way selection switch and a second end of the gain halving capacitor, and a second end of the second complement bit capacitor are respectively connected to a negative going reference voltage, a capacitance value of the second complement bit capacitor is equal to a capacitance value of a first bit capacitor in the N−1 bit second capacitors, capacitance values of the N−1 bit second capacitors are sequentially increased by a power of 2 from small to large according to the number of bits, and a capacitance value of the gain halving capacitor is a sum of the capacitance values of the N−1 bit second capacitors and the second complement bit capacitor, where N is an integer greater than 1; and   a digital coding unit connected to output the ends of the first digital control logic unit and the second digital control logic unit.   
     
     
         10 . An electronic device, comprising a device body, and an integrated circuit according to  claim 9 , wherein the integrated circuit is provided in the device body. 
     
     
         11 . The integrated circuit according to  claim 9 , wherein the analog input voltage is a differential voltage; and two first capacitor arrays are provided and correspondingly connected to a positive going input voltage and a negative going input voltage in the differential voltage. 
     
     
         12 . The integrated circuit according to  claim 11 , wherein the residue amplifier is a differential amplifier having two input ends correspondingly connected to residual voltages output from the two first capacitor arrays. 
     
     
         13 . The integrated circuit according to  claim 12 , wherein the differential amplifier has two output ends; and two second capacitor arrays are provided and correspondingly connected to the two output ends of the differential amplifier. 
     
     
         14 . The integrated circuit according to  claim 9 , wherein the residue amplifier has an amplification factor being an (M−2) th  power of 2. 
     
     
         15 . The integrated circuit according to  claim 9 , wherein the second end of each first capacitor is further connected to a common mode voltage through the multi-way selection switch. 
     
     
         16 . The integrated circuit according to  claim 9 , wherein the second end of each second capacitor is further connected to a common mode voltage through the multi-way selection switch. 
     
     
         17 . The integrated circuit according to  claim 9 , further comprising a sample and hold circuit connected to the analog input voltage and the first digital-to-analog converter.