Self-aligned gate isolation for multi-directional gate layouts in quantum and semiconductor devices
Abstract
One embodiment of the invention provides a method for fabricating a self-aligned gate structure comprising forming at least one first trench having a first width and at least one second trench having a second width in a gate structure comprising a first metallic gate layer. The first width is smaller than the second width. The method comprises depositing at least one conformal dielectric layer on the first metallic gate layer. The dielectric layer completely fills the first trench and partially fills the second trench, such that a portion of the second trench is unfilled. The method comprises depositing a conformal second metallic gate layer on the dielectric layer. The second metallic gate layer fills the unfilled portion of the second trench. The method comprises removing portions of the second metallic gate layer to expose the dielectric layer. Remaining portions of the second metallic gate layer include self-aligned metallic gate electrodes.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A method for fabricating a self-aligned gate structure with multiple metallic gate electrodes, comprising:
forming at least one first trench having a first width in a gate structure comprising a first metallic gate layer of metallic gate electrodes; forming at least one second trench having a second width in the gate structure, wherein the first width is smaller than the second width; depositing at least one conformal dielectric layer on the first metallic gate layer, wherein the at least one conformal dielectric layer completely fills the at least one first trench, and the at least one conformal dielectric layer partially fills the at least one second trench, such that a portion of the at least one second trench is unfilled; depositing a conformal second metallic gate layer of metallic gate electrodes on the at least one conformal dielectric layer, wherein the conformal second metallic gate layer fills up the unfilled portion of the at least one second trench; and removing one or more portions of the conformal second metallic gate layer to expose the at least one conformal dielectric layer; wherein one or more remaining portions of the conformal second metallic gate layer include self-aligned metallic gate electrodes.
2 . The method of claim 1 , wherein a thickness of the at least one conformal dielectric layer is larger than a first value that is equal to half of the first width, and the thickness of the at least one conformal dielectric layer is smaller than a second value that is equal to half of the second width.
3 . The method of claim 1 , removing the one or more portions of the conformal second metallic gate layer comprises a blanket etch.
4 . The method of claim 1 , wherein removing the one or more portions of the conformal second metallic gate layer comprises chemical-mechanical polishing (CMP).
5 . The method of claim 1 , wherein the method isolates or terminates the self-aligned metallic gate electrodes.
6 . The method of claim 1 , wherein the self-aligned gate structure is one-dimensional (1D).
7 . The method of claim 1 , wherein the self-aligned gate structure is two-dimensional (2D).
8 . The method of claim 1 , wherein the self-aligned gate structure comprises at least one array of channels, fins, or functional sites that run in at least one linear section.
9 . The method of claim 8 , wherein the self-aligned gate structure further comprises at least one additional array of metallic gate electrodes that run in a different direction relative to the at least one array of channels, fins, or functional sites.
10 . The method of claim 8 , further comprising:
fabricating one or more intersection elements, wherein each intersection element is between two or more channels, fins, or functional sites that run in different directions.
11 . A structure comprising:
a first metallic gate electrode located on at least one channel; a second metallic gate electrode separated from the first metallic gate electrode by a first width; a first dielectric layer located between the first metallic gate electrode and the second metallic gate electrode, wherein the first dielectric layer fills an area between the first metallic gate electrode and the second metallic gate electrode; a third metallic gate electrode separated from the second metallic gate electrode by a second width, wherein the second width is greater than the first width; a second dielectric layer located between the second metallic gate electrode and third metallic gate electrode, wherein the second dielectric layer has a substantially uniform thickness along sidewalls of each metallic gate electrode and the at least one channel; and a self-aligned metallic gate electrode located between sidewalls of the second dielectric layer.
12 . The structure of claim 11 , wherein a thickness of the second dielectric layer is larger than half the first width.
13 . The structure of claim 11 , wherein the self-aligned metallic gate electrode is isolated or terminated.
14 . The structure of claim 11 , wherein the first metallic gate electrode, the second metallic gate electrode, and the third metallic gate electrode are substantially parallel.
15 . The structure of claim 11 , wherein the first metallic gate electrode and the second metallic gate electrode are not parallel.
16 . The structure of claim 11 , wherein the structure comprises at least one channel, fin, or functional site that runs in at least one linear section.
17 . The structure of claim 16 , wherein the structure further comprises at least one metallic gate electrode that runs in a different direction relative to the at least one channel, fin, or functional site.
18 . The structure of claim 16 , wherein the structure further comprises an intersection element.Join the waitlist — get patent alerts
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