Display device

Abstract

A display device A display device includes a display panel including a plurality of pixel rows and a plurality of pixel columns arranged to display an image; a data driver comprising a plurality of source drive integrated circuits (ICs) respectively connected to one or more pixel columns among the plurality of pixel columns and configured to supply a data signal to the plurality of pixel rows; and a timing controller configured to supply image data and a data control signal to the data driver, wherein the timing controller includes a general purpose input-output (GPIO) pin connected to digital block power down enable (DBDEN) pins provided in each of the plurality of source drive ICs in a point-to-multipoint way and outputs a DBDEN signal disabling to at least some of the plurality of source drive ICs.

What is claimed is: 
     
         1 . A display device comprising:
 a display panel including a plurality of pixel rows and a plurality of pixel columns arranged to display an image;   a data driver comprising a plurality of source drive integrated circuits (ICs) respectively connected to one or more pixel columns among the plurality of pixel columns and configured to supply a data signal to the plurality of pixel rows; and   a timing controller configured to supply image data and a data control signal to the data driver,   wherein the timing controller includes a general purpose input-output (GPIO) pin connected to digital block power down enable (DBDEN) pins provided in each of the plurality of source drive ICs in a point-to-multipoint way and outputs a DBDEN signal disabling to at least some of the plurality of source drive ICs,   wherein each of the plurality of source drive IC comprises:   a receiver connected to an interface wiring pair and receiving a control packet and a data packet from the timing controller;   a logic unit configured to process the control packet and the data packet; and   a logic gate connected to the DBDEN pin and an output of the logic unit, and configured to operate and output a DBDEN signal and an output signal of the logic unit to the receiver.   
     
     
         2 . The display device of  claim 1 , wherein the timing controller transmits the control packet indicating whether to disable the source drive ICs through the interface wiring pair connected to the data driver upon the DBDEN signal enabled. 
     
     
         3 . The display device of  claim 2 , wherein the plurality of source drive ICs is selectively disabled based on 2-bit pseudo control data included in the control packet and the DBDEN signal. 
     
     
         4 . The display device of  claim 1 , wherein the logic unit is configured to output a logic high signal to stop operating the receiver upon the control packet indicating disability. 
     
     
         5 . The display device of  claim 4 , wherein the logic gate outputs a logic high signal upon the DBDEN signal of a logical high-level supplied to the DBDEN pin and the logic high signal output from the logic unit. 
     
     
         6 . The display device of  claim 5 , wherein the receiver comprises an operational amplifier configured to receive an output of the logic gate as a driving voltage, and amplify and output an input signal of the interface wiring pair. 
     
     
         7 . The display device of  claim 6 , wherein the operational amplifier is disabled and stops the output upon the logic high signal received from the logic gate. 
     
     
         8 . The display device of  claim 1 , wherein the logic unit comprises:
 a digital circuit configured to perform a digital logic function required for driving the display panel; and   an analog circuit configured to generate an analog output based on an output of the digital circuit.   
     
     
         9 . The display device of  claim 8 , wherein the logic unit disables the digital circuit upon the control packet indicating the disability. 
     
     
         10 . The display device of  claim 1 , wherein the timing controller is configured to disable the source drive IC connected to the pixel column comprising two or more pixel rows by outputting the DBDEN signal to the plurality of source drive ICs, upon the two or more pixel rows displaying a same grayscale. 
     
     
         11 . The display device of  claim 10 , wherein the timing controller is configured to transmit the control packet for indicating disability to the source drive IC connected to the pixel column comprising the two or more pixel rows through the interface wiring pair. 
     
     
         12 . A display device comprising:
 a display panel comprising a plurality of pixel rows and a plurality of pixel columns arranged to display an image;   a plurality of source drive integrated circuits (ICs) respectively connected to one or more pixel columns and configured to supply a data signal to the pixel rows; and   a timing controller configured to disable at least one source drive ICs connected to two or more pixel rows upon the two or more pixel rows displaying a same grayscale,   wherein the timing controller transmits a control packet for indicating the at least one source drive ICs to be disabled and a digital block power down enable (DBDEN) signal to the plurality of source drive ICs upon the at least one source drive ICs being disabled,   wherein each of the plurality of source drive IC comprises:   a receiver connected to an interface wiring pair and receiving the control packet and a data packet from the timing controller;   a logic unit configured to process the control packet and the data packet; and   a logic gate connected to the DBDEN pin and an output of the logic unit, and configured to operate and output a DBDEN signal and an output signal of the logic unit to the receiver.   
     
     
         13 . The display device of  claim 12 , wherein the control packet comprises 2-bit pseudo control data indicating whether each of the plurality of source drive ICs is disabled. 
     
     
         14 . The display device of  claim 13 , wherein the control packet comprises a value of ‘11’ for the at least one source drive IC to be disabled, and a value of ‘00’ for remaining source drive ICs. 
     
     
         15 . The display device of  claim 13 , wherein a disability of the plurality of source drive ICs is determined based on the 2-bit pseudo control data included in the control packet upon receiving the DBDEN signal. 
     
     
         16 . The display device of  claim 15 , wherein the plurality of source drive ICs comprises:
 a digital circuit configured to perform a digital logic function required for driving the display panel; and   an analog circuit configured to generate an analog output based on an output of the digital circuit,   wherein the digital circuit is disabled based on the control data.   
     
     
         17 . The display device of  claim 12 , wherein the timing controller is connected to each of the plurality of source drive ICs through an interface wiring pair, and
 wherein the timing controller is connected to DBDEN pins provided in the plurality of source drive ICs in a point-to-multipoint way through a general purpose input-output (GPIO) pin.   
     
     
         18 . The display device of  claim 17 , wherein the DBDEN signal is output through the GPIO pin, and the control packet is output through the interface wiring pair.