Method of interleaved processing on a general-purpose computing core

Abstract

A method of “interleaved processing” (IP) is proposed which generalizes the functional principle of memory interleaving by extending the interleaved memory system into the processor chip and prepending each write access to one of the extended interleaved memory banks by a data transforming operation. The method opens a new dimension of large scale software parallelization and is implemented in autonomous processing units called “parallel processing channels” (PPC) that integrate processor and memory at a very low machine balance—which solves the memory wall problem—and execute on-chip machine transactions at a 1 Flop/cycle throughput. If computing systems are linearly performance scalable and capable of pipelined execution of very large and complex HPC workloads. They have unique performance advantages in strided vector, tensor, and data set operations; for relevant HPC workload types, up to 10×-100× per-Watt single-processor performance gains compared to today's technologies are expected.

The invention claimed is: 
     
         1 . A programmable data processing apparatus, comprising
 a combined data processing and storage unit comprising   a data processing unit comprising at least one arithmetic logic unit capable of executing data-transforming operations specified by an instruction set architecture of the apparatus, including at least one of arithmetic, logic, or other foundational data-transforming operations on data of all data types supported by the apparatus as per the instruction set architecture of the apparatus, and   a storage unit for storing data and code pertaining to said operations, wherein at least one part of a memory of the storage unit comprises a parallel memory that includes at least one plurality of memory systems wherein, the memory systems of the plurality are random access memory systems, and jointly provide at least one unified memory address space of the plurality which is accessible through the instruction set architecture of the apparatus, and in which accesses to said plurality can be executed at memory addresses of said unified memory address space, and   a programmable control unit for executing further operations specified by the instruction set architecture, including at least one of a pointer dereference, data fetch, data store, comparison, instruction fetch, decode, dispatch or branch,   the control unit being adapted to, under control by code fetched from the storage unit in at least one operational mode of the apparatus, fetch operand data from the parallel memory of the storage unit and to control the data processing unit by specifying at least one of the data-transforming operations to be performed, the operand data to be processed by said data-transforming operations, and destination addresses for results of said data-transforming operations,   characterized in that   the apparatus is configured to, in at least one operational mode, execute a parallel random access to the parallel memory comprising at least one plurality of accesses to the parallel memory executed in parallel, wherein per each access individually, as per the instruction set architecture of the apparatus, a memory system of the parallel memory and a memory address located within said memory system are selected, said selection defining the memory access location for the execution of the data access.   
     
     
         2 . The apparatus of  claim 1 , wherein the data transforming operations include at least one transaction which causes the arithmetic logic unit to write the value of at least one operand directly to the parallel memory of the storage unit. 
     
     
         3 . The apparatus of  claim 1 , wherein at least one arithmetic logic unit of the at least one arithmetic logic unit is connected to a port of the control unit. 
     
     
         4 . The apparatus of  claim 1 , wherein at least one memory system of the parallel memory is connected to at least one arithmetic logic unit of the at least one arithmetic logic unit via at least one port. 
     
     
         5 . The apparatus of  claim 1 , wherein at least one memory system of the parallel memory is partitioned into a set of memory subsystems. 
     
     
         6 . The apparatus of  claim 1 , wherein at least one memory system of the parallel memory is further adapted to exchange data with at least one of an external data source or data sink. 
     
     
         7 . The apparatus of  claim 1 , wherein the control unit is further connected to at least one memory system of the parallel memory via at least one data port. 
     
     
         8 . The apparatus of  claim 1 , wherein the control unit, by means of an interleaved memory abstraction layer, is adapted to access the parallel memory as interleaved logical memory such that any interleaved logical memory address uniquely specifies a memory system of the parallel memory and an address for the memory access within said specified memory system. 
     
     
         9 . The apparatus of  claim 8 , wherein the control unit comprises an address decoder implementing the interleaved memory abstraction layer. 
     
     
         10 . The apparatus of  claim 1 , wherein the apparatus is configured to, in at least one operational mode of the apparatus, write the at least one result of the data-transforming operations directly to at least one destination address within one of the memory systems of the parallel memory. 
     
     
         11 . The apparatus of  claim 1 , wherein, in at least one operational mode of the apparatus, the data processing unit is adapted to execute at least one very long transaction word comprising a set of parallel transactions issued by the control unit to the data processing unit, each transaction specifying at least one of at least one data-transforming operation to be performed, at least one operand data to be processed by the at least one data-transforming operation, and at least one destination address in the parallel memory of the apparatus for results of the at least one data-transforming operation. 
     
     
         12 . The apparatus of  claim 1 , wherein a total number of memory systems of the parallel memory is prime. 
     
     
         13 . A method of using the apparatus of  claim 8 , wherein by means of a further pipelined memory abstraction layer, at least one virtual data flow is generated, each virtual data flow being controlled by an address transformation defined within a memory block allocated from the interleaved logical memory forming a pipeline such that an index associated with the pipeline is either subtracted from or added to a relative address located within the pipeline, the address transformation yielding a latch address. 
     
     
         14 . The method of  claim 13 , wherein a modulo operation is further included in said address transformation. 
     
     
         15 . The method of  claim 13 , wherein in at least one operational mode of the apparatus, said latch address is used, as per the instruction set architecture of the apparatus, to specify a memory address for the parallel random access to the parallel memory. 
     
     
         16 . The method of  claim 13 , wherein the pipeline is associated with at least one software loop for either incrementing or decrementing the index associated with the pipeline. 
     
     
         17 . The method of  claim 13 , wherein the pipeline is executed by a dedicated thread. 
     
     
         18 . The method of  claim 13 , wherein multiple pipelines communicate with one another. 
     
     
         19 . The method of  claim 18 , wherein the communicating pipelines form a network. 
     
     
         20 . The method of  claim 13 , wherein control flow information is embedded into data streams processed by or communicated between pipelines. 
     
     
         21 . The method of  claim 20 , wherein the control flow information is embedded into a one of the data streams by augmenting each data word of said one of the data streams by a control tag, each augmented data word being stored, processed and communicated as a whole, and the control tag comprising a combination of bits including at least one of a bit controlling loop termination, a bit controlling conditional execution of operations on the augmented data word, and a bit indicating that the data word contains further control information. 
     
     
         22 . The method of  claim 13 , wherein said pipeline is used as an addressable stack of data referenced relatively to a top of said stack, said address transformation yielding a virtual register address. 
     
     
         23 . The method of  claim 13 , wherein address decoder hardware is used to translate latch addresses to logical addresses.