Integrated circuits and methods for power delivery

Abstract

An integrated circuit includes a first power rail, a second power rail, and a power tap cell. The first power rail is at a first side of the integrated circuit. The second power rail is at a second side of the integrated circuit. The first and second sides are on opposite sides of at least a complementary field effect transistor. The power tap cell is coupled to the first power rail and the second power rail and configured to provide power from the first power rail to the second power rail.

What is claimed is: 
     
       1. An integrated circuit, comprising:
 a first power rail extending along a first direction at a first side of the integrated circuit; 
 a second power rail extending along a second direction at a second side of the integrated circuit, the first and second sides being on opposite sides of at least a complementary field effect transistor; and 
 a power tap cell extending along a third direction and coupled between the first power rail and the second power rail and configured to provide power from the first power rail to the second power rail, 
 wherein the first direction, the second direction, and the third direction are respectively along first, second, and third axes of a three-dimensional coordinate system. 
 
     
     
       2. The integrated circuit of  claim 1 , further comprising:
 one or more complementary field effect transistors, 
 wherein:
 the first side is a back side of the integrated circuit; 
 the second side is a front side of the integrated circuit; and 
 the first power rail is configured to provide a negative voltage level to the integrated circuit. 
 
 
     
     
       3. The integrated circuit of  claim 1 , wherein the power tap cell comprises a first via, a metal layer, a second via, a first metal diffusion (MD) layer, and a third via, wherein:
 the first via is coupled between the first power rail and the metal layer; 
 the metal layer is coupled between the first via and the second via; 
 the second via is coupled between the metal layer and the first MD layer; 
 the first MD layer is coupled between the second via and the third via; 
 the third via is coupled between the first MD layer and a second MD layer; and 
 the second MD layer is coupled to the second power rail through a fourth via. 
 
     
     
       4. The integrated circuit of  claim 3 , wherein the metal layer is a first metal layer, the integrated circuit further comprising:
 a second metal layer and a third metal layer at the first side, 
 wherein:
 the first power rail is in the third metal layer at the first side; 
 the first side is a back side of the integrated circuit; and 
 the second side is a front side of the integrated circuit. 
 
 
     
     
       5. The integrated circuit of  claim 4 , further comprising:
 a third power rail at the first side, 
 wherein:
 the third power rail is in the second metal layer at the first side; 
 the first power rail is configured to provide a negative voltage level to the integrated circuit; and 
 the third power rail is configured to provide a positive voltage level to the integrated circuit. 
 
 
     
     
       6. The integrated circuit of  claim 3 , wherein the metal layer is a first metal layer, the integrated circuit further comprising:
 a metal line in a second metal layer at the second side, 
 wherein:
 the second power rail includes the metal line in the second metal layer at the second side; 
 the first side is a back side of the integrated circuit; and 
 the second side is a front side of the integrated circuit. 
 
 
     
     
       7. The integrated circuit of  claim 1 , wherein the power tap cell comprises a feed-through via coupled between the first power rail and the second power rail. 
     
     
       8. The integrated circuit of  claim 7 , further comprising:
 a first metal layer and a second metal layer at the first side; and 
 a third metal layer at the second side, 
 wherein:
 the first power rail is in the second metal layer at the first side; 
 the second power rail is in the third metal layer at the second side; 
 the first side is a back side of the integrated circuit; and 
 the second side is a front side of the integrated circuit. 
 
 
     
     
       9. The integrated circuit of  claim 8 , further comprising:
 a third power rail at the first side, 
 wherein:
 the third power rail is in the first metal layer at the first side; 
 the first power rail is configured to provide a negative voltage level to the integrated circuit; and 
 the third power rail is configured to provide a positive voltage level to the integrated circuit. 
 
 
     
     
       10. The integrated circuit of  claim 1 , wherein the power tap cell comprises a feed-through via and a metal line in a metal layer at the first side, wherein:
 the feed-through via is coupled between the first power rail and the second power rail through the metal line; and 
 the metal line is provided with the power from the first power rail. 
 
     
     
       11. The integrated circuit of  claim 10 , wherein the metal layer is a first metal layer at the first side and the integrated circuit further comprises:
 a second metal layer at the first side, 
 wherein:
 the first power rail is in the second metal layer at the first side; 
 the first side is a back side of the integrated circuit; and 
 the second side is a front side of the integrated circuit. 
 
 
     
     
       12. The integrated circuit of  claim 11 , further comprising:
 a first metal line in a third metal layer and a second metal line in a fourth metal layer at the second side; and 
 a via coupled between the first metal line and the second metal line at the second side, 
 wherein the second power rail includes the first metal line in the third metal layer at the second side. 
 
     
     
       13. The integrated circuit of  claim 1 , wherein the power tap cell comprises a through-silicon via (TSV) and a metal line in a metal layer at the first side, wherein:
 the TSV is coupled between the first power rail and the second power rail through the metal line; and 
 the metal line is provided with the power from the first power rail. 
 
     
     
       14. The integrated circuit of  claim 13 , wherein the metal layer is a first metal layer at the first side, and the integrated circuit further comprises:
 a second metal layer at the first side, 
 wherein:
 the first power rail is in the second metal layer at the first side; 
 the first side is a back side of the integrated circuit; and 
 the second side is a front side of the integrated circuit. 
 
 
     
     
       15. The integrated circuit of  claim 14 , further comprising:
 a first metal line in a third metal layer and a second metal line in a fourth metal layer at the second side; and 
 a via coupled between the first metal line and the second metal line at the second side, 
 wherein the second power rail includes the second metal line in the fourth metal layer at the second side. 
 
     
     
       16. The integrated circuit of  claim 1 , wherein the power tap cell comprises a through-silicon via (TSV), wherein the TSV is coupled between the first power rail and the second power rail. 
     
     
       17. The integrated circuit of  claim 16 , further comprising:
 a metal layer at the first side; and 
 a metal layer at the second side, 
 wherein:
 the first power rail is in the metal layer at the first side; 
 the second power rail is in the metal layer at the second side; 
 the first side is a back side of the integrated circuit; and 
 the second side is a front side of the integrated circuit. 
 
 
     
     
       18. An integrated circuit, comprising:
 a plurality of complementary field effect transistors; 
 a first power rail extending along a first direction at a first side of the integrated circuit; 
 a second power rail extending along a second direction at a second side of the integrated circuit, the first and second sides being on opposite sides of the plurality of complementary field effect transistors; and 
 a through-silicon via (TSV) extending along a third direction and coupled between the first power rail at the first side and the second power rail at the second side, 
 wherein the first direction, the second direction, and the third direction are respectively along first, second, and third axes of a three-dimensional coordinate system. 
 
     
     
       19. The integrated circuit of  claim 18 , further comprising:
 a metal line in a metal layer at the second side, 
 wherein the TSV extends through the metal line. 
 
     
     
       20. An integrated circuit, comprising:
 a plurality of complementary field effect transistors; 
 a first power rail extending along a first direction at a first side of the integrated circuit; 
 a second power rail extending along a second direction at a second side of the integrated circuit, the first and second sides being on opposite sides of the plurality of complementary field effect transistors; and 
 a feed-through via extending along a third direction and coupled between the first power rail at the first side and the second power rail at the second side, 
 wherein the first direction, the second direction, and the third direction are respectively along first, second, and third axes of a three-dimensional coordinate system.