Semiconductor device

Abstract

A semiconductor device may include bit line structures on a substrate, a contact plug structure on the substrate between the bit line structures, and a capacitor electrically connected to the contact plug structure. The contact plug structure may include a first contact plug, a second contact plug, and a third contact plug sequentially stacked. An upper surface of the second contact plug includes an upper recess. The third contact plug may fill the upper recess, and may protrude above the upper recess. An upper surface of the third contact plug may be higher than a top surface of the bit line structures.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 bit line structures on a substrate; 
 a contact plug structure on the substrate between the bit line structures, the contact plug structure including a first contact plug, a second contact plug, and a third contact plug sequentially stacked; and 
 a capacitor electrically connected to the contact plug structure, 
 wherein an upper surface of the second contact plug includes an upper recess, 
 wherein the third contact plug fills the upper recess and protrudes above the upper recess, and an upper surface of the third contact plug is higher than a top surface of the bit line structures, and 
 wherein the second contact plug includes a second barrier metal pattern comprising a first material and a second metal pattern comprising a second material different from the first material, the second barrier metal pattern being on and contacting sidewalls and a bottom of the second metal pattern. 
 
     
     
       2. The semiconductor device of  claim 1 ,
 wherein an upper portion of each of the bit line structures includes a capping pattern including an insulation material, and 
 wherein a first sidewall of the third contact plug contacts a sidewall of the capping pattern in the bit line structure. 
 
     
     
       3. The semiconductor device of  claim 2 , wherein the first sidewall of the third contact plug contacting the capping pattern has a smaller slope than a second sidewall of the third contact plug contacting the second contact plug with respect to an upper surface of the third contact plug. 
     
     
       4. The semiconductor device of  claim 2 , wherein in a portion lower than a top surface of the capping pattern, a width of the third contact plug is gradually decreased downward. 
     
     
       5. The semiconductor device of  claim 1 , wherein a top surface of the second contact plug is lower than the top surface of the bit line structures. 
     
     
       6. The semiconductor device of  claim 1 , wherein the first contact plug includes polysilicon, and the second contact plug and the third contact plug include a metal. 
     
     
       7. The semiconductor device of  claim 1 , wherein a top surface of the second barrier metal pattern is lower than a top surface of the second metal pattern. 
     
     
       8. The semiconductor device of  claim 1 , wherein the third contact plug includes a third barrier metal pattern and a third metal pattern, and the third barrier metal pattern is formed on sidewalls and a bottom of the third metal pattern. 
     
     
       9. The semiconductor device of  claim 8 , wherein the third barrier metal pattern is formed on a surface of the upper recess of the second contact plug. 
     
     
       10. The semiconductor device of  claim 1 , further comprising a metal silicide pattern between the first contact plug and the second contact plug. 
     
     
       11. The semiconductor device of  claim 1 , further comprising a spacer structure on sidewalls of the bit line structures. 
     
     
       12. The semiconductor device of  claim 11 , wherein the spacer structure comprises:
 a first spacer covering the sidewalls of the bit line structures; 
 a second spacer covering an outer wall of the first spacer; and 
 a third spacer covering an outer wall of the second spacer. 
 
     
     
       13. The semiconductor device of  claim 11 ,
 wherein the third contact plug contacts an upper portion of the bit line structures and an upper portion of the spacer structure adjacent thereto, and 
 wherein upper sidewalls of the bit line structures and the spacer structure contacting the third contact plug has a smaller slope than opposite upper sidewalls of the bit line structures and the spacer structure. 
 
     
     
       14. A semiconductor device, comprising:
 bit line structures on a substrate; 
 a contact plug structure on the substrate between the bit line structures, the contact plug structure including a first contact plug including polysilicon, a second contact plug including a metal on the first contact plug, and a third contact plug including a metal on the second contact plug sequentially stacked; and 
 a capacitor electrically connected to the contact plug structure, wherein a top surface of the second contact plug is lower than a top surface of the bit line structures, 
 wherein an upper surface of the third contact plug is higher than the top surface of the bit line structures, and a lowermost surface of the third contact plug is lower than the top surface of the second contact plug, 
 wherein a first sidewall of the third contact plug contacts a sidewall of a first bit line structure of the bit line structure, 
 wherein the second contact plug includes a second barrier metal pattern comprising a first material and a second metal pattern comprising a second material different from the first material, the second barrier metal pattern being on and contacting sidewalls and a bottom of the second metal pattern, and 
 wherein the third contact plug contacts the second barrier metal pattern and the second metal pattern. 
 
     
     
       15. The semiconductor device of  claim 14 , wherein the first sidewall of the third contact plug contacting the sidewall of the first bit line structure has a smaller slope than a second sidewall of the third contact plug contacting the second contact plug. 
     
     
       16. The semiconductor device of  claim 14 , further comprising a spacer structure on sidewalls of the first bit line structure. 
     
     
       17. The semiconductor device of  claim 16 ,
 wherein the third contact plug contacts an upper portion of the first bit line structure and an upper portion of the spacer structure adjacent thereto, and 
 wherein upper sidewalls of the first bit line structure and the spacer structure contacting the third contact plug has a smaller slope than opposite upper sidewalls of the first bit line structure and the spacer structure. 
 
     
     
       18. The semiconductor device of  claim 14 ,
 wherein a top surface of the second barrier metal pattern is lower than a top surface of the second metal pattern. 
 
     
     
       19. A semiconductor device, comprising:
 a substrate including an active pattern defined by an isolation pattern; 
 gate structures buried in the active pattern and the isolation pattern of the substrate; 
 bit line structures on the substrate; 
 a contact plug structure on the active pattern between the bit line structures, the contact plug structure including a first contact plug including polysilicon, a second contact plug including a metal on the first contact plug, and a third contact plug including a metal on the second contact plug sequentially stacked; and 
 a capacitor electrically connected to the contact plug structure, 
 wherein the second contact plug includes a second barrier metal pattern comprising a first material and a second metal pattern comprising a second material different from the first material, the second barrier metal pattern being on and contacting sidewalls and a bottom of the second metal pattern, 
 wherein the third contact plug contacts a sidewall of a first bit line structure of the bit line structures and upper surfaces of the second barrier metal pattern and the second metal pattern of the second contact plug, and 
 wherein both sidewalls of the third contact plug have slopes different from each other, in a cross-sectional view. 
 
     
     
       20. The semiconductor device of  claim 1 , wherein the third contact plug contacts the second barrier metal pattern and the second metal pattern.