Semiconductor structure and manufacturing method thereof

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a substrate, and forming a sacrificial dielectric layer on the substrate; patterning a part of the sacrificial dielectric layer along a first direction, and forming a plurality of first trenches arranged at intervals along a second direction in the sacrificial dielectric layer; patterning a part of the sacrificial dielectric layer at bottoms of the first trenches and a part of the substrate below the part of the sacrificial dielectric layer, and forming a plurality of second trenches arranged at intervals below the first trenches, wherein the second trench has a preset depth in the substrate; forming a protective layer on sidewalls of the first trenches and sidewalls of the second trenches; and forming bit line structures in the first trenches and the second trenches.

The invention claimed is: 
     
       1. A method of manufacturing a semiconductor structure, comprising:
 providing a substrate, and forming a sacrificial dielectric layer on the substrate; 
 patterning a part of the sacrificial dielectric layer along a first direction, and forming a plurality of first trenches arranged at intervals along a second direction in the sacrificial dielectric layer; 
 patterning a part of the sacrificial dielectric layer at bottoms of the first trenches and a part of the substrate below the part of the sacrificial dielectric layer, and forming a plurality of second trenches arranged at intervals below the first trenches, wherein the second trench has a preset depth in the substrate; 
 forming a protective layer on sidewalls of the first trenches and sidewalls of the second trenches; and 
 forming bit line structures in the first trenches and the second trenches. 
 
     
     
       2. The method according to  claim 1 , wherein the forming a sacrificial dielectric layer on the substrate comprises:
 forming a first sacrificial dielectric layer on the substrate; and 
 forming a second sacrificial dielectric layer on the first sacrificial dielectric layer. 
 
     
     
       3. The method according to  claim 2 , wherein the patterning a part of the sacrificial dielectric layer along a first direction, and forming a plurality of first trenches arranged at intervals along a second direction in the sacrificial dielectric layer comprises: patterning the second sacrificial dielectric layer along the first direction, and forming the first trenches arranged at intervals along the second direction in the second sacrificial dielectric layer, wherein the bottoms of the first trenches expose a part of the first sacrificial dielectric layer. 
     
     
       4. The method according to  claim 3 , wherein the patterning a part of the sacrificial dielectric layer at bottoms of the first trenches and a part of the substrate below the part of the sacrificial dielectric layer, and forming a plurality of second trenches arranged at intervals below the first trenches comprises: patterning the part of the first sacrificial dielectric layer exposed by the first trenches and a part of the substrate at a bottom of the part of the first sacrificial dielectric layer, and forming the second trenches in the first sacrificial dielectric layer and the substrate, wherein in a direction perpendicular to the substrate, the second trench has a first depth. 
     
     
       5. The method according to  claim 2 , wherein the forming a protective layer on sidewalls of the first trenches and sidewalls of the second trenches comprises:
 forming a first protective layer covering both surfaces of the first trenches and surfaces of the second trenches; 
 forming a second protective layer on a surface of the first protective layer; 
 forming a third protective layer on a surface of the second protective layer; and 
 removing a part of the first protective layer, a part of the second protective layer, and a part of the third protective layer that are at bottom surfaces of the first trenches and bottom surfaces of the second trenches, to expose a part of the substrate at bottoms of the second trenches, and retaining a part of the first protective layer, a part of the second protective layer, and a part of the third protective layer that are on the sidewalls of the first trenches and the sidewalls of the second trenches, wherein the part of the first protective layer, the part of the second protective layer, and the part of the third protective layer that are retained form the protective layer. 
 
     
     
       6. The method according to  claim 5 , wherein the forming bit line structures in the first trenches and the second trenches comprises:
 forming a bit line contact layer in the second trenches; 
 forming a bit line conductive layer in the first trenches, wherein the bit line conductive layer is connected to the bit line contact layer; and 
 forming a bit line insulating layer in the first trenches and on the bit line conductive layer; wherein 
 the bit line contact layer, the bit line conductive layer, and the bit line insulating layer form the bit line structures. 
 
     
     
       7. The method according to  claim 6 , wherein in a direction perpendicular to the substrate, the second trench has a first depth, a thickness of the bit line contact layer is not smaller than the preset depth of the second trench in the substrate and is not greater than the first depth, and a top surface of the bit line insulating layer is not higher than a top surface of the second sacrificial dielectric layer. 
     
     
       8. The method according to  claim 7 , after the forming bit line structures, the method further comprises:
 forming a mask layer on the top surface of the second sacrificial dielectric layer, the top surface of the bit line insulating layer, and a top surface of the protective layer; 
 patterning the mask layer, and forming a plurality of pattern holes arranged at intervals in the mask layer, wherein the pattern hole exposes a part of a top surface of a part of the second sacrificial dielectric layer between adjacent two of the bit line structures in the second direction, and a top surface of a part of the second sacrificial dielectric layer between adjacent two of the pattern holes in the first direction is covered by the mask layer; 
 patterning the second sacrificial dielectric layer and the first sacrificial dielectric layer below the second sacrificial dielectric layer along the pattern holes, and forming third trenches in the first sacrificial dielectric layer and the second sacrificial dielectric layer, wherein a bottom surface of the third trench exposes a part of a surface of a part of the substrate between adjacent two of the bit line structures in the second direction; and 
 forming capacitive contact structures in the third trenches. 
 
     
     
       9. The method according to  claim 7 , after the forming bit line structures, the method further comprises:
 forming a mask layer on the top surface of the second sacrificial dielectric layer, the top surface of the bit line insulating layer, and a top surface of the protective layer; 
 patterning the mask layer, and forming a plurality of pattern holes arranged at intervals in the mask layer, wherein the pattern hole exposes a part of a top surface of a part of the second sacrificial dielectric layer between adjacent two of the bit line structures in the second direction and a part of a top surface of a part of the protective layer between the adjacent two of the bit line structures in the second direction, and a top surface of a part of the second sacrificial dielectric layer between adjacent two of the pattern holes in the first direction is covered by the mask layer; 
 patterning the second sacrificial dielectric layer and the first sacrificial dielectric layer below the second sacrificial dielectric layer along the pattern holes, and forming third trenches in the first sacrificial dielectric layer and the second sacrificial dielectric layer, and removing the part of the second protective layer that is retained in the protective layer, wherein a bottom surface of the third trench exposes a part of a surface of a part of the substrate between adjacent two of the bit line structures in the second direction; and 
 forming capacitive contact structures in the third trenches. 
 
     
     
       10. The method according to  claim 8 , wherein the patterning the mask layer, and forming a plurality of pattern holes arranged at intervals in the mask layer comprises:
 forming a first mask layer, wherein the first mask layer is provided with a plurality of first patterns extending along the first direction and arranged at intervals along the second direction, and the first pattern covers the bit line structure; 
 forming a second mask layer on the first mask layer, wherein the second mask layer is provided with a plurality of second patterns extending along the second direction and arranged at intervals along the first direction; and 
 transferring the second patterns into the first mask layer, removing a part of the first mask layer that is not covered by the first patterns and the second patterns, and forming the pattern holes. 
 
     
     
       11. The method according to  claim 10 , wherein the first mask layer and the second sacrificial dielectric layer have a same material, and a remaining part of the first mask layer is removed while the patterning the second sacrificial dielectric layer and the first sacrificial dielectric layer below the second sacrificial dielectric layer along the pattern holes, and forming the third trenches in the first sacrificial dielectric layer and the second sacrificial dielectric layer. 
     
     
       12. The method according to  claim 8 , further comprising: removing the part of the second protective layer that is retained through a drying etching process after the patterning the second sacrificial dielectric layer along the pattern holes, and patterning the first sacrificial dielectric layer. 
     
     
       13. The method according to  claim 8 , wherein the forming capacitive contact structures in the third trenches comprises:
 forming a capacitive contact layer on a surface of a part of the substrate at bottoms of the third trenches; and 
 forming a metal connection layer on the capacitive contact layer. 
 
     
     
       14. The method according to  claim 9 , wherein the second protective layer and the second sacrificial dielectric layer have a same material, and the first protective layer and the third protective layer have a same material. 
     
     
       15. The method according to  claim 9 , wherein the patterning the mask layer, and forming a plurality of pattern holes arranged at intervals in the mask layer comprises:
 forming a first mask layer, wherein the first mask layer is provided with a plurality of first patterns extending along the first direction and arranged at intervals along the second direction, and the first pattern covers the bit line structure; 
 forming a second mask layer on the first mask layer, wherein the second mask layer is provided with a plurality of second patterns extending along the second direction and arranged at intervals along the first direction; and 
 transferring the second patterns into the first mask layer, removing a part of the first mask layer that is not covered by the first patterns and the second patterns, and forming the pattern holes. 
 
     
     
       16. The method according to  claim 9 , wherein the forming capacitive contact structures in the third trenches comprises:
 forming a capacitive contact layer on a surface of a part of the substrate at bottoms of the third trenches; and 
 forming a metal connection layer on the capacitive contact layer. 
 
     
     
       17. A semiconductor structure, manufactured by using the method according to  claim 1 .