Charge pumps, logic circuits including charge pumps, logic devices including logic circuits, and methods of operating logic circuits

Abstract

A GaN logic circuit may include an input node receiving an input voltage, a first pull up transistor pulling up an output voltage in response to the input voltage, and a first depletion mode transistor having a first gate to which a first gate voltage is applied and a second gate to which a second gate voltage is applied. The first depletion mode transistor may control the first pull up transistor in response to a gate voltage difference between the first gate voltage and the second gate voltage. The logic device may further include a capacitor having a first end coupled to the first depletion mode transistor and a second end coupled to the first pull up transistor.

The invention claimed is: 
     
       1. A charge pump for a GaN logic circuit, comprising:
 a first transistor configured to pull down an output voltage in response to an input voltage having a first level and pull up the output voltage in response to the input voltage having a second level; and 
 a second transistor having a first gate, a second gate, and an output terminal coupled to a gate of the first transistor and being configured to provide a first saturation current therethrough, 
 wherein the second transistor is configured to adjust the first saturation current therethrough by a second saturation current flowing into the first gate of the second transistor in response to the input voltage having the second level. 
 
     
     
       2. The charge pump of  claim 1 , wherein the second transistor is a depletion mode transistor, and the output terminal of the depletion mode transistor is controlled by a gate voltage difference between a first gate voltage applied to the first gate and a second gate voltage applied to the second gate, the charge pump further comprising:
 a capacitor having a first end coupled to the second transistor and a second end coupled to the first transistor. 
 
     
     
       3. The charge pump of  claim 2 , wherein the depletion mode transistor adjusts a pinch off voltage thereof and the first saturation current in response to the gate voltage difference. 
     
     
       4. The charge pump of  claim 3 , wherein the output terminal of the depletion mode transistor is a source coupled to the gate of the first transistor, and the depletion mode transistor further has a drain coupled to the first end of the capacitor. 
     
     
       5. The charge pump of  claim 1 , wherein the second transistor is a depletion mode transistor, the charge pump further comprising:
 a first current source configured to discharge the second saturation current to ground when the input voltage has the first level, and to provide the second saturation current to the depletion mode transistor to adjust the gate voltage difference when the input voltage has the second level. 
 
     
     
       6. The charge pump of  claim 5 , wherein the depletion mode transistor is a first depletion mode transistor, and
 wherein the first current source includes:
 a first resistor having a first end and a second end, the second end coupled to the first gate of the first depletion mode transistor; and 
 a second depletion mode transistor having a source coupled to the first end of the first resistor, a gate coupled to the second end of the first resistor, and a drain coupled to the drain of the first depletion mode transistor. 
 
 
     
     
       7. The charge pump of  claim 6 , further comprising:
 a second current source configured to discharge the first saturation current to the ground when the input voltage has the first level. 
 
     
     
       8. The charge pump of  claim 7 , wherein the second current source includes:
 a second resistor having a first end and a second end; and 
 a third depletion mode transistor having a drain coupled to the source of the first depletion mode transistor, a source coupled to the first end of the second resistor, a gate coupled to the second end of the second resistor. 
 
     
     
       9. The charge pump of  claim 1 , wherein the second transistor has a drain coupled to a source of a third transistor. 
     
     
       10. A GaN logic circuit, comprising:
 an input node configured to receive an input voltage; 
 a first pull up transistor configured to pull up an output voltage in response to the input voltage; 
 a first depletion mode transistor having a first gate to which a first gate voltage is applied and a second gate to which a second gate voltage is applied, the first depletion mode transistor configured to control the first pull up transistor by adjusting a first saturation current through the first depletion mode transistor in response to a gate voltage difference between the first gate voltage and the second gate voltage; 
 a capacitor having a first end coupled to the first depletion mode transistor and a second end coupled to the first pull up transistor; and 
 a first current source configured to discharge a second saturation current to ground when the input voltage has a first level, and to provide the second saturation current to the first depletion mode transistor to adjust the gate voltage difference when the input voltage has a second level. 
 
     
     
       11. The GaN logic circuit of  claim 10 , wherein the first depletion mode transistor adjusts a pinch off voltage thereof in response to the gate voltage difference, and provides the first saturation current to pull down the output voltage to a third level when the input voltage has the first level and to pull up the output voltage to a fourth level when the input voltage has the second level, the first level being higher than the second level. 
     
     
       12. The GaN logic circuit of  claim 11 , wherein the first depletion mode transistor keeps each of the pinch off voltage and the first saturation current substantially constant to pull down the output voltage to the third level when the input voltage has the first level, and increases each of the pinch off voltage and the first saturation current substantially linearly with the gate voltage difference to pull up the output voltage to the fourth level when the input voltage has the second level. 
     
     
       13. The GaN logic circuit of  claim 11 , wherein a power supply voltage has the fourth level, and the first pull up transistor is further configured to receive the first saturation current from the first depletion transistor and to pull up the output voltage to the power supply voltage when the input voltage has the second level, the circuit further comprising:
 a second pull up transistor configured to pull up a voltage at the first end of the capacitor to the power supply voltage when the input voltage has the first level, and make the first end of the capacitor float when the input voltage has the second level. 
 
     
     
       14. The GaN logic circuit of  claim 13 , wherein the first pull up transistor has a drain coupled to the power supply voltage, a gate coupled to a source of the first depletion mode transistor, and a source coupled to the output node, and
 wherein the second pull up transistor has a drain coupled to the power supply voltage, a gate coupled to the input node, and a source coupled to the first end of the capacitor. 
 
     
     
       15. The GaN logic circuit of  claim 11 , wherein the power supply voltage is a first power supply voltage, the circuit further comprising:
 a second pull up transistor configured to pull up a voltage at the first end of the capacitor to a second power supply voltage when the input voltage has the first level, and make the first end of the capacitor float when the input voltage has the second level, the second power supply voltage having a level different from that of the first power supply voltage. 
 
     
     
       16. The GaN logic circuit of  claim 10 , wherein the first current source includes:
 a first resistor having a first end and a second end, the second end coupled to the first gate of the first depletion mode transistor; and 
 a second depletion mode transistor having a source coupled to the first end of the first resistor, a gate coupled to the second end of the first resistor, and a drain coupled to a drain of the first depletion mode transistor. 
 
     
     
       17. The GaN logic circuit of  claim 16 , wherein the first resistor has a resistance value in a range from 10 kohm (kΩ) to 1 Megaohm (MΩ). 
     
     
       18. The GaN logic circuit of  claim 16 , further comprising:
 a first pull down transistor having a drain coupled to the second end of the first resistor, a gate coupled to the input node, and a source coupled to the ground. 
 
     
     
       19. The GaN logic circuit of  claim 10 , further comprising:
 a second current source configured to discharge the first saturation current to the ground when the input voltage has the first level. 
 
     
     
       20. A logic device, comprising:
 a logic gate configured to receive a pair of input signals and performs a logic operation on the received input signals to generate an intermediate signal; and 
 a GaN inverter configured to receive the intermediate signal and generate an output signal, the inverter comprising:
 an input node configured to receive the intermediate signal; 
 a first pull up transistor configured to pull up the output signal in response to the intermediate signal; 
 a depletion mode transistor having a first gate to which a first gate voltage applies and a second gate to which a second gate voltage applies, the depletion mode transistor configured to control the first pull up transistor in response to a gate voltage difference between the first gate voltage and the second gate voltage; 
 a capacitor having a first end coupled to the depletion mode transistor and a second end coupled to the first pull up transistor; and 
 a second pull up transistor configured to pull up a voltage at the first end of the capacitor to a power supply voltage when the intermediate signal has a first level, and make the first end of the capacitor float when the intermediate signal has a second level.