Method and apparatus for etching a semiconductor substrate in a plasma etch chamber

Abstract

Methods and apparatus for etching a substrate in a plasma etch chamber are provided. In one example, the method includes exposing a substrate disposed on a substrate supporting surface of a substrate support to a plasma within a processing chamber, and applying a voltage waveform to an electrode disposed in the substrate support while the substrate is exposed to the plasma during a plurality of macro etch cycles. Each macro etch cycle includes a first macro etch period and a second macro etch period. The macro etch period includes a plurality of micro etch cycles. Each micro etch cycle has a bias power on (BPON) period and a bias power off (BPOFF) period, wherein a duration of the BPON period being less than a duration of the BPOFF period. Bias power is predominantly not applied to the electrode during the second macro etch period.

What is claimed is: 
     
       1. A method for etching a substrate in a plasma etch chamber, the method comprising:
 exposing the substrate disposed on a substrate supporting surface of a substrate support to a plasma within the processing chamber; and 
 applying a voltage waveform to an electrode disposed in the substrate support while the substrate is exposed to the plasma during a plurality of macro etch cycles, each macro etch cycle including a first macro etch period and a second macro etch period, the macro etch period comprises a plurality of micro etch cycles, each micro etch cycle having a bias power on (BPON) period and a bias power off (BPOFF) period, a duration of the BPON period being less than a duration of the BPOFF period, and bias power predominantly not applied to the electrode during the second macro etch period. 
 
     
     
       2. The method of  claim 1 , wherein the BPON period of one of the micro etch cycles is less than 45% of the BPOFF period. 
     
     
       3. The method of  claim 1 , wherein the BPON period of one of the micro etch cycles is between about 10% and about 45% of the BPOFF period. 
     
     
       4. The method of  claim 1 , wherein the plurality of macro etch cycles includes a first macro etch cycle occurring prior to a second macro etch cycle, and wherein a BPON period of one of the micro etch cycles of the first macro etch cycle is greater than a BPON period of one of the micro etch cycles of the second macro etch cycle. 
     
     
       5. The method of  claim 1 , wherein a frequency of the macro etch cycles of the plurality of macro etch cycles decreases as the substrate is etched. 
     
     
       6. The method of  claim 1 , wherein the frequency of the macro etch cycles is between about 2 to about 100 Hz. 
     
     
       7. The method of  claim 1 , wherein a frequency of the micro etch cycles is between about 25 to about 500 KHz. 
     
     
       8. The method of  claim 7 , wherein the frequency of the macro etch cycles is between about 2 to about 100 Hz. 
     
     
       9. The method of  claim 1 , wherein each micro etch cycle is at least an order of magnitude less than the macro etch cycle. 
     
     
       10. The method of  claim 1  further comprising:
 forming the plasma from a processing gas comprising carbon and at least one halogen. 
 
     
     
       11. The method of  claim 10 , wherein a dielectric material is removed from the substrate during the BPON period. 
     
     
       12. The method of  claim 11 , wherein the dielectric material is an oxide material, nitride material, or a stack of oxide and nitride layer pairs. 
     
     
       13. The method of  claim 11 , wherein the dielectric material includes at least one oxide layer and at least one nitride layer. 
     
     
       14. The method of  claim 11 , wherein the processing gas one or both of C x F z  and C x H y F z , wherein x, y and z are integers. 
     
     
       15. A method for etching a substrate in a plasma etch chamber, the method comprising:
 forming a plasma from a processing gas containing carbon and at least one halogen; 
 exposing a dielectric layer disposed on the substrate to the plasma within the plasma etch chamber; and 
 applying bias power to an electrode disposed in a substrate support supporting the substrate within the plasma etch chamber while exposed to the plasma during a plurality of macro etch cycles until an end point is reached, each macro etch cycle including a first macro etch period and a second macro etch period, the macro etch period comprises a plurality of micro etch cycles, each micro etch cycle having a bias power on (BPON) period and a bias power off (BPOFF) period, a duration of the BPON period being less than a duration of the BPOFF period, bias power predominantly not applied to the electrode during the second macro etch period, wherein in at least macro etch cycle: 
 the BPON period is at least two orders of magnitude shorter in duration than the first macro etch period; and 
 the BPOFF period is at least two orders of magnitude shorter in duration than the second macro etch period. 
 
     
     
       16. The method of  claim 15 , wherein the BPON period of one of the micro etch cycles is less than 45% of the BPOFF period. 
     
     
       17. The method of  claim 15 , wherein the BPON period of one of the micro etch cycles is between about 10% and about 45% of the BPOFF period. 
     
     
       18. The method of  claim 15 , wherein the plurality of macro etch cycles includes a first macro etch cycle occurring prior to a second macro etch cycle, and wherein a BPON period of one of the micro etch cycles of the first macro etch cycle is greater than a BPON period of one of the micro etch cycles of the second macro etch cycle. 
     
     
       19. The method of  claim 15 , wherein a frequency of the macro etch cycles of the plurality of macro etch cycles decreases as the substrate is etched. 
     
     
       20. A plasma etch chamber comprising a chamber body having an interior volume;
 a substrate support disposed in the interior volume of the chamber body, the substrate support configured to retain a substrate thereon during processing, the substrate support having an electrode; 
 a bias power control system coupled to the electrode; 
 a gas panel configured to provide a processing gas to the interior volume; and 
 a controller configured to:
 maintain a plasma within the processing chamber formed from the processing gas; and 
 apply a voltage waveform to the electrode while the substrate disposed on the substrate support is exposed to the plasma during a plurality of macro etch cycles, each macro etch cycle including a first macro etch period and a second macro etch period, the macro etch period comprises a plurality of micro etch cycles, each micro etch cycle having a bias power on (BPON) period and a bias power off (BPOFF) period, a duration of the BPON period being less than a duration of the BPOFF period, and bias power is predominantly not applied to the electrode during the second macro etch period.