Method for reading memory device and memory device

Abstract

A method for reading a memory device is provided. The memory device includes a plurality of word lines and a plurality of multi-bit memory cells connected to the plurality of word lines, and each of the multi-bit memory cells is configured such that a stored value of the multi-bit memory cell is read through multi-level preset read voltages. The method includes: defining at least one read offset for each of the multi-level preset read voltages respectively, selecting at least one of the multi-level preset read voltages as at least one sampling voltage, reading a multi-bit memory cell on an adjacent word line of a to-be-read multi-bit memory cell, and setting at least one offset flag, each representing a size of a respective one of at least one read offset, according to a sampling reading value of each of the at least one sampling voltage.

The invention claimed is: 
     
       1. A method for reading a memory device, wherein the memory device comprises a plurality of word lines and a plurality of multi-bit memory cells connected to the plurality of word lines, each of the multi-bit memory cells being configured such that a stored value of the multi-bit memory cell is read through multi-level preset read voltages, the method comprising:
 reading a multi-bit memory cell on an adjacent word line of a to-be-read multi-bit memory cell by using at least one sampling voltage; 
 determining at least one offset flag, each representing a size of a respective one of at least one read offset according to a sampling read value of each of the at least one sampling voltage, wherein the at least one sampling voltage is at least one of the multi-level preset read voltages, the at least one sampling voltage comprises N sampling voltages, each of the multi-level preset read voltages corresponds to N+1 read offsets, and N is a positive integer greater than or equal to 2; and 
 reading the to-be-read multi-bit memory cell, according to the multi-level preset read voltages and the at least one read offset of each of the multi-level preset read voltages, each corresponding to a respective one of the at least one offset flag. 
 
     
     
       2. The method of  claim 1 , wherein each of the plurality of multi-bit memory cells is configured to be programmed in one of multi-level threshold voltages, the multi-bit memory cell falls into one of N+1 sampling reading value partitions due to differences of the multi-level threshold voltages, and each of sampling reading value partitions corresponds to a respective one of the at least one offset flag. 
     
     
       3. The method of  claim 2 , wherein determining the at least one offset flag comprises:
 obtaining, by using the N sampling voltages, a reading value of the multi-bit memory cell on the adjacent word line of the to-be-read multi-bit memory cell; 
 classifying, according to the reading value, the multi-bit memory cell on the adjacent word line of the to-be-read multi-bit memory cell into one of the N+1 sampling reading value partitions; and 
 determining an offset flag corresponding to the classified sampling reading value partition. 
 
     
     
       4. The method of  claim 3 , wherein reading the to-be-read multi-bit memory cell comprises:
 determining a current read offset of a preset read voltage of a level corresponding to the offset flag; and 
 performing reading of the to-be-read multi-bit memory cell according to a sum of the preset read voltage of the level corresponding to the offset flag and the current read offset. 
 
     
     
       5. The method of  claim 1 , further comprising:
 defining N+1 read offsets corresponding to each of the multi-level preset read voltages. 
 
     
     
       6. The method of  claim 1 , wherein the offset flag is represented by log 2 (N+1) bits. 
     
     
       7. The method of  claim 1 , wherein the read offset comprises one of a voltage offset value or a voltage offset time. 
     
     
       8. The method of  claim 1 , wherein the adjacent word line is a word line immediately subsequent to a word line on which the to-be-read multi-bit memory cell is located. 
     
     
       9. The method of  claim 1 , wherein the multi-bit memory cell comprises a three-bit memory cell, and the memory device comprises a low page, an intermediate page, and a high page; and
 the method is applicable to an operation of reading the low page, an operation of reading the intermediate page, and an operation of reading the high page. 
 
     
     
       10. A memory device, comprising:
 a memory cell array and a peripheral circuit coupled to the memory cell array, wherein 
 the memory cell array comprises a plurality of word lines and a plurality of multi-bit memory cells connected to the plurality of word lines; and 
 the peripheral circuit is configured to:
 read a stored value of each of the multi-bit memory cells through multi-level preset read voltages; 
 read a multi-bit memory cell on an adjacent word line of a to-be-read multi-bit memory cell by using at least one sampling voltage; 
 determine at least one offset flag, each representing a size of a respective one of at least one read offset according to a sampling read value of each of the at least one sampling voltage; and 
 read the to-be-read multi-bit memory cell, according to the multi-level preset read voltages and the at least one read offset of each of the multi-level preset read voltages, each corresponding to a respective one of the at least one offset flag, 
 wherein the at least one sampling voltage is at least one of the multi-level preset read voltages, the at least one sampling voltage comprises N sampling voltages, each of the multi-level preset read voltages corresponds to N+1 read offsets, and N is a positive integer greater than or equal to 2. 
 
 
     
     
       11. The memory device of  claim 10 , wherein each of the plurality of multi-bit memory cells is configured to be programmed in one of multi-level threshold voltages, the multi-bit memory cell falls into one of N+1 sampling reading value partitions due to differences of the multi-level threshold voltages, and each of sampling reading value partitions corresponds to a respective one of the at least one offset flag. 
     
     
       12. The memory device of  claim 11 , wherein the peripheral circuit comprises:
 a sampling reading value obtaining unit, configured to:
 obtain, by using the N sampling voltages, a reading value of the multi-bit memory cell on the adjacent word line of the to-be-read multi-bit memory cell; 
 classify, according to the reading value, the multi-bit memory cell on the adjacent word line of the to-be-read multi-bit memory cell into one of the N+1 sampling reading value partitions; and 
 determine an offset flag corresponding to the classified sampling reading value partition. 
 
 
     
     
       13. The memory device of  claim 12 , wherein the peripheral circuit is configured to:
 determine a current read offset of a preset read voltage of a level corresponding to the offset flag; and 
 perform reading of the to-be-read multi-bit memory cell according to a sum of the preset read voltage of the level corresponding to the offset flag and the current read offset. 
 
     
     
       14. The memory device of  claim 10 , wherein the offset flag is stored in a program block latch of the memory device. 
     
     
       15. The memory device of  claim 14 , wherein the program block latch has log 2 (N+1) data bits for storing the offset flag.