Software-defined compute nodes on multi-SoC architectures

Abstract

Provided are methods for forming redundant node configurations in a multi-systems-on-a-chip environment. Each system-on-a-chip can include one or processors and memories independent of other systems-on-a-chip and in communication via a cache coherent fabric. To facilitate rapid and extensible reconfiguration, various systems-on-a-chip from the multi-systems-on-a-chip environment can be configured into a redundant node configuration, with each logical node implemented by one or more of the systems-on-a-chip. Each system-on-a-chip within a logical node can be configured to utilize a shared memory space, such as by transparent mirroring of logical memory addresses. Across nodes, systems-on-a-chip can communicate using a device-to-device protocol such as a non-transparent bridge. My reconfiguration of communication between systems-on-a-chip, the multi-systems-on-a-chip environment can be reconfigured to represent a variety of redundant configurations. In one example, a multi-systems-on-a-chip environment can be configured to support safe, resilient operation of an autonomous vehicle.

What is claimed is: 
     
       1. A computer-implemented method comprising:
 obtaining a specification of a redundant node configuration for a multiprocessor-system-on-a-chip architecture, wherein the redundant node configuration specifies at least a first logical computing node implementing redundant operations using at least two multiprocessor-systems-on-a-chip, each of the at least two multiprocessor-systems-on-a-chip comprising multiple processors; 
 initializing, based on the specification of the redundant node configuration, communications between the at least two multiprocessor-systems-on-a-chip to form the redundant node configuration implementing redundant operations using the at least two multiprocessor-systems-on-a-chip; and 
 executing target computer-executable instructions on the redundant node configuration corresponding to the at least two multiprocessor-systems-on-a-chip in communication according to the specification of the redundant node configuration. 
 
     
     
       2. The computer-implemented method of  claim 1 , wherein the at least two multiprocessor-systems-on-a-chip communicate via a cache coherent fabric. 
     
     
       3. The computer-implemented method of  claim 1 , wherein each multiprocessor-system-on-a-chip is associated with a distinct memory, and wherein the at least two multiprocessor-systems-on-a-chip share data between respective distinct memories via transparent mirroring of logical memory addresses. 
     
     
       4. The computer-implemented method of  claim 1  further comprising:
 obtaining a specification of an alternate redundant node configuration; 
 reconfiguring communications between the at least two multiprocessor-systems-on-a-chip to form the alternate redundant node configuration; and 
 executing target computer-executable instructions on the alternate redundant node configuration. 
 
     
     
       5. The computer-implemented method of  claim 1 , wherein the least two multiprocessor-systems-on-a-chip comprises at least three multiprocessor-systems-on-a-chip, wherein the redundant node configuration implements at least two logical computing nodes implementing redundant operations, and wherein a first logical computing node of the at least two logical computing nodes is implemented using at least two of the at least three multiprocessor-systems-on-a-chip. 
     
     
       6. The computer-implemented method of  claim 5 , wherein a second logical computing node of the at least two logical computing nodes redundantly implements safety-critical operations of the first logical computing node. 
     
     
       7. The computer-implemented method of  claim 6 , wherein the at least two logical computing nodes comprise a third logical computing node implementing the safety-critical operations of the first logical computing node. 
     
     
       8. The computer-implemented method of  claim 7 , wherein the first, second, and third logical computing nodes are configured to implement the safety-critical operations in a quorum-based manner. 
     
     
       9. The computer-implemented method of  claim 1 , wherein the target computer-executable instructions implement operations of an autonomous vehicle. 
     
     
       10. The computer-implemented method of  claim 1 , wherein the at least two multiprocessor-systems-on-a-chip are physically interconnected via a mesh topology network. 
     
     
       11. The computer-implemented method of  claim 1 , wherein at least one of the multiprocessor-systems-on-a-chip implements a deterministic processing architecture. 
     
     
       12. The computer-implemented method of  claim 1 , wherein initializing communications between at least two multiprocessor-systems-on-a-chip to form the redundant node configuration comprises creating a shared memory space among physical memory of the at least two multiprocessor-systems-on-a-chip. 
     
     
       13. The computer-implemented method of  claim 1 , wherein initializing communications between at least two multiprocessor-systems-on-a-chip to form the redundant node configuration comprises executing middleware software during initialization of the at least two multiprocessor-systems-on-a-chip and halting execution of the middleware software prior to executing the target computer-executable instructions. 
     
     
       14. The computer-implemented method of  claim 1  further comprising:
 detecting a failure on a first multiprocessor-system-on-a-chip of the at least two multiprocessor-systems-on-a-chip; 
 initializing communications between a second multiprocessor-system-on-a-chip of the at least two multiprocessor-systems-on-a-chip and a third multiprocessor-system-on-a-chip to re-form the redundant node configuration; and 
 executing the target computer-executable instructions on the reformed redundant node configuration. 
 
     
     
       15. A system-on-a-chip, comprising:
 memory storing computer-executable instructions; and 
 at least one processor configured to:
 obtain a specification of a redundant node configuration for the system-on-a-chip, wherein the redundant node configuration specifies at least a first logical computing node implementing redundant operations using at least the system-on-a-chip and at least one other system-on-a-chip; 
 initialize, based on the specification of the redundant node configuration, the system-on-a-chip by initiating communications with the at least one other system-on-a-chip to form the redundant node configuration implementing the redundant operations using at least the system-on-a-chip and at least one other system-on-a-chip; and 
 execute target computer-executable instructions on the system-on-a-chip in accordance with the redundant node configuration corresponding to at least the system-on-a-chip and at least one other system-on-a-chip in communication according to the specification of the redundant node configuration. 
 
 
     
     
       16. The system-on-a-chip of  claim 15 , wherein the system-on-a-chip is associated with a memory distinct from memory of the at least one other system-on-a-chip, and wherein initiating communications with the at least one other system-on-a-chip to form the redundant node configuration comprises initializing transparent mirroring of logical memory addresses with the at least one other system-on-a-chip. 
     
     
       17. The system-on-a-chip of  claim 15 , wherein the at least one processor is further configured to:
 detect a failure on the at least one other system-on-a-chip; 
 initialize communications with an additional system-on-a-chip to re-form the redundant node configuration; and 
 execute the target computer-executable instructions on the reformed redundant node configuration. 
 
     
     
       18. One or more non-transitory computer-readable media comprising instructions that, when executed on a system-on-a-chip, cause the system-on-a-chip:
 obtain a specification of a redundant node configuration for the system-on-a-chip, wherein the redundant node configuration specifies at least a first logical computing node implementing redundant operations using at least the system-on-a-chip and at least one other system-on-a-chip; 
 initialize, based on the specification of the redundant node configuration, the system-on-a-chip by initiating communications with the at least one other system-on-a-chip to form the redundant node configuration implementing the redundant operations using at least the system-on-a-chip and at least one other system-on-a-chip; and 
 execute target computer-executable instructions on the system-on-a-chip in accordance with the redundant node configuration corresponding to at least the system-on-a-chip and at least one other system-on-a-chip in communication according to the specification of the redundant node configuration. 
 
     
     
       19. The one or more non-transitory computer-readable media of  claim 18 , wherein the instructions further cause the system-on-a-chip to initialize communications between the system-on-a-chip and an additional system-on-a-chip via a device-to-device protocol. 
     
     
       20. The one or more non-transitory computer-readable media of  claim 18 , wherein the target computer-executable instructions implement operations of an autonomous vehicle.