Memory device with semiconductor layer on isolation structure

Abstract

A semiconductor device includes: a semiconductor substrate; a transistor formed on the semiconductor substrate; a first insulating layer adjacent to the transistor in a first direction along a main surface of the semiconductor substrate, the first insulating layer being formed toward an inside of the semiconductor substrate; a first conductive layer connected to a gate of the transistor, a part of the first conductive layer being opposed to the first insulating layer; a second insulating layer disposed between the first insulating layer and the first conductive layer; and a first semiconductor layer disposed between the second insulating layer and the first conductive layer.

What is claimed is: 
     
       1. A semiconductor memory device comprising:
 a semiconductor substrate; 
 a plurality of conductive films arranged in a stacking direction intersecting with a main surface of the semiconductor substrate; 
 a semiconductor column extending in the stacking direction and being opposed to the plurality of conductive films; 
 an electric charge accumulating layer disposed between the plurality of conductive films and the semiconductor column; 
 a transistor formed on the semiconductor substrate; 
 a first insulating layer adjacent to the transistor in a first direction along the main surface of the semiconductor substrate, the first insulating layer extending in the stacking direction, at least a part of the first insulating layer being formed inside of the semiconductor substrate; 
 a first conductive layer connected to a gate of the transistor, a part of the first conductive layer being opposed to the first insulating layer; 
 a second insulating layer disposed between the first insulating layer and the first conductive layer; and 
 a first semiconductor layer disposed between the second insulating layer and the first conductive layer, wherein 
 a source of the transistor is electrically connected to one of the plurality of conductive films. 
 
     
     
       2. The semiconductor memory device according to  claim 1 , wherein
 a width in the first direction of the second insulating layer is greater than a width in the first direction of the first insulating layer. 
 
     
     
       3. The semiconductor memory device according to  claim 1 , wherein
 a width in a second direction of the second insulating layer is greater than a width in the second direction of the first conductive layer, the second direction intersecting with the first direction and being along the main surface of the semiconductor substrate. 
 
     
     
       4. The semiconductor memory device according to  claim 1 , wherein
 the transistor includes:
 a third insulating layer disposed on the semiconductor substrate; 
 a second semiconductor layer disposed on the third insulating layer; and 
 a first impurity layer and a second impurity layer disposed in the semiconductor substrate, wherein 
 the first impurity layer is disposed on one side in a second direction with respect to the second semiconductor layer, the second direction intersecting with the first direction and being along the main surface of the semiconductor substrate, and the second impurity layer is disposed on the other side in the second direction with respect to the second semiconductor layer. 
 
 
     
     
       5. The semiconductor memory device according to  claim 4 , wherein
 the second insulating layer is disposed on the first insulating layer and the second semiconductor layer. 
 
     
     
       6. The semiconductor memory device according to  claim 4 , wherein
 a first transistor and a second transistor having same configurations as the transistor are disposed adjacent to one another in the first direction, and 
 the first insulating layer is disposed between the first transistor and the second transistor. 
 
     
     
       7. The semiconductor memory device according to  claim 6 , wherein
 the second insulating layer has a rectangular shape viewed from a direction intersecting with the main surface of the semiconductor substrate and covers a part of the first insulating layer and parts of the second semiconductor layers on both sides in the first direction of the first insulating layer. 
 
     
     
       8. The semiconductor memory device according to  claim 4 , wherein
 the second semiconductor layer has a width in the second direction at a first position adjacent to the first insulating layer greater than a width of the second semiconductor layer in the second direction at a second position farther from the first insulating layer than the first position. 
 
     
     
       9. The semiconductor memory device according to  claim 8 , wherein
 the second semiconductor layer has an H-type shape viewed from a direction intersecting with the main surface of the semiconductor substrate. 
 
     
     
       10. The semiconductor memory device according to  claim 4 , further comprising
 a passive element, wherein 
 the passive element includes:
 a second conductive layer having parts separated in a direction along the main surface of the semiconductor substrate, the second conductive layer being formed in a same layer as the first conductive layer; 
 a fourth insulating layer disposed between the separated parts of the second conductive layer, the fourth insulating layer being formed in a same layer as the second insulating layer; 
 a third semiconductor layer disposed between the second conductive layer and the fourth insulating layer, the third semiconductor layer being formed in a same layer as the first semiconductor layer; and 
 a fourth semiconductor layer connected to at least one of the separated parts of the second conductive layer, the fourth semiconductor layer being formed in a same layer as the second semiconductor layer.