Semiconductor device with silicide gate fill structure

Abstract

A semiconductor process system etches gate metals on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an atomic layer etching process. The process system then uses the selected process conditions data for the next etching process.

The invention claimed is: 
     
       1. An integrated circuit, comprising:
 an interlevel dielectric layer; 
 a first transistor including:
 a plurality of semiconductor nanosheets corresponding to channels of the first transistor; 
 a first trench formed in the interlevel dielectric layer; 
 a first gate dielectric positioned on a bottom of the first trench and on sidewalls of the first trench; and 
 a first gate electrode, including:
 a first gate metal having a first material positioned in direct physical contact with a first portion of a sidewall of the first gate dielectric in the first trench; 
 a second gate metal having a second material positioned on the first gate metal and in direct physical contact with a second portion of the sidewall of the first gate dielectric in the first trench above the first portion of the sidewall of the first gate dielectric, wherein the second material is different than the first material; 
 a third gate metal positioned on the second gate metal and in direct physical contact with a third portion of the sidewall of the first gate dielectric in the first trench above the second portion of the sidewall of the first gate dielectric, the second gate metal being positioned between the first gate metal and the third gate metal, wherein the first gate metal, the second gate metal, and the third gate metal surround the semiconductor nanosheets; 
 first silicide positioned in the first trench above the first gate metal; and 
 a first conductive gate fill material positioned over the first gate metal and first silicide in the first trench, wherein the first conductive gate fill material extends to a higher vertical level within the first trench than the first gate metal, wherein the third gate metal, the first conductive gate fill material, the first silicide, and the first gate dielectric extend to a same vertical height within the first trench, a highest surface of the first gate metal is below a lowest surface of the first silicide in the first trench, wherein a highest surface of the second gate metal is below a lowest surface of the first silicide in the first trench. 
 
 
 
     
     
       2. The integrated circuit of  claim 1 , wherein the first silicide is titanium silicide. 
     
     
       3. The integrated circuit of  claim 1 , wherein the first gate dielectric surrounds the semiconductor nanosheets. 
     
     
       4. The integrated circuit of  claim 1 , wherein the first gate dielectric includes hafnium. 
     
     
       5. The integrated circuit of  claim 1 , further comprising:
 a second transistor including: 
 a second trench formed in the interlevel dielectric layer; 
 a second gate dielectric positioned on a bottom of the second trench and on sidewalls of the second trench; and 
 a second gate electrode, including:
 a second silicide; and 
 a second conductive gate fill material positioned in the second trench, the second conductive gate fill material of the second transistor is positioned closer to the bottom of the second trench than the first conductive gate fill material of the first transistor is positioned to the bottom of the first trench. 
 
 
     
     
       6. The integrated circuit of  claim 5 , wherein the first transistor has a higher threshold voltage than the second transistor. 
     
     
       7. The integrated circuit of  claim 1 , wherein the first gate metal is titanium nitride. 
     
     
       8. The integrated of  claim 1 , wherein the first conductive gate fill material includes tungsten. 
     
     
       9. An integrated circuit, comprising:
 a plurality of first semiconductor nanosheets corresponding to channel regions of a first transistor; 
 an interlevel dielectric layer; 
 a first trench in the interlevel dielectric layer over first semiconductor nanosheets; 
 a first gate dielectric on a bottom of the first trench and on sidewalls of the first trench; 
 a first gate metal having a first material positioned in direct physical contact with a first portion of a sidewall of the first gate dielectric in the first trench; 
 a second gate metal having a second material positioned on the first gate metal and in contact with a second portion of the sidewall of the first gate dielectric in the first trench above the first portion of the sidewall of the first gate dielectric, wherein the second material is different than the first material; 
 a third gate metal positioned on the second gate metal and in direct physical contact with the a third portion of the sidewall of the first gate dielectric in the first trench above the second portion of the sidewall of the first gate dielectric, the second gate metal being positioned between the first gate metal and the third gate metal, wherein the first gate metal, the second gate metal, and the third gate metal surround the first semiconductor nanosheets; 
 a first silicide on the third gate metal in the first trench, wherein a lowest surface of the first silicide is higher in the first trench than a highest surface of the first gate metal and a highest surface of the second gate metal; and 
 a first conductive gate fill material over the third gate metal, the second gate metal, and the first silicide, wherein a top surface of the first silicide is substantially coplanar with a top surface of the third gate metal and with a top surface of the first conductive gate fill material, wherein the first gate metal has a substantially uniform vertical thickness and the second gate metal has a non-uniform vertical thickness. 
 
     
     
       10. The integrated circuit of  claim 9 , wherein the first silicide incudes titanium silicide. 
     
     
       11. The integrated circuit of  claim 9 , further comprising:
 a plurality of second semiconductor nanosheets corresponding to channel regions of a second transistor; 
 a second trench in the interlevel dielectric layer over the plurality of second semiconductor nanosheets; 
 a second gate dielectric on a bottom of the second trench; 
 a second silicide over the second gate dielectric in the second trench; 
 a second conductive gate fill material in the second trench, wherein the second conductive gate fill material is positioned closer to the bottom of the second trench than the first conductive gate fill material is to the bottom of the first trench. 
 
     
     
       12. The integrated circuit of  claim 11 , wherein the first transistor has a higher threshold voltage than the second transistor. 
     
     
       13. The integrated circuit of  claim 9 , wherein the first gate metal is titanium nitride. 
     
     
       14. The integrated circuit of  claim 9 , wherein the first gate dielectric surrounds the first semiconductor nanosheets. 
     
     
       15. An integrated circuit, comprising:
 an interlevel dielectric layer; 
 a first trench in the first interlevel dielectric layer; 
 a second trench in the second interlevel dielectric layer; 
 a first transistor including:
 a plurality of first semiconductor nanosheets below the first trench and corresponding to channel regions of the first transistor; and 
 a first gate structure in the first trench above the first semiconductor nanosheets including:
 a first gate dielectric positioned on a bottom of the first trench and on sidewalls of the first trench; 
 a first gate metal having a first material positioned in direct physical contact with a first portion of a sidewall of the first gate dielectric in the first trench; 
 a second gate metal having a second material positioned on the first gate metal and in direct physical contact with a second portion of the sidewall of the first gate dielectric above the first portion of the sidewall of the first gate dielectric, wherein the second material is different than the first material; 
 a third gate metal positioned on the second gate metal and in direct physical contact with a third portion of the sidewall of the first gate dielectric in the first trench above the second portion of the sidewall of the first gate dielectric, the second gate metal being positioned between the first gate metal and the third gate metal, wherein the first gate metal, the second gate metal, and the third gate metal surround the semiconductor nanosheets; 
 a first silicide above the first gate metal and the second gate metal, wherein a lowest surface of the first silicide is higher than a highest surface of the first gate metal and a highest surface the second gate metal; and 
 a first conductive gate fill material on the first silicide, wherein the first conductive gate fill material extends to a higher vertical level above the first semiconductor nanosheets than does first gate metal; and 
 
 
 a second transistor including:
 a plurality of second semiconductor nanosheets below the second trench and corresponding to channel regions of the second transistor; and 
 a second gate structure above the second semiconductor nanosheets including:
 a second gate dielectric in the second trench; 
 a fourth gate metal in contact with the second gate dielectric in the second trench, wherein the fourth gate metal extends higher above the second semiconductor nanosheets than the first gate metal extends above the first semiconductor nanosheets; 
 a second silicide above the fourth gate metal, wherein a lowest surface of the second silicide is higher than a highest surface of the second layer of the fourth gate metal in the second trench; and 
 a second conductive gate fill material in the second trench over the fourth gate metal and the second silicide, wherein the second conductive gate fill material is positioned closer to the second nanosheets than the first conductive gate fill material is positioned to the first nanosheets. 
 
 
 
     
     
       16. The integrated circuit of  claim 15 , wherein the first gate dielectric includes hafnium. 
     
     
       17. The integrated circuit of  claim 16 , wherein the first transistor has a higher threshold voltage than the second transistor. 
     
     
       18. The integrated circuit of  claim 15 , wherein the third gate metal has a top surface that is substantially coplanar with a top surface of the first silicide. 
     
     
       19. The integrated circuit of  claim 18 , wherein the first gate structure includes a glue layer of titanium nitride between the first silicide and the first conductive gate fill material. 
     
     
       20. The integrated circuit of  claim 15 , wherein the fourth gate metal has the second material.