Semiconductor device

Abstract

An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on the number of write operations. The semiconductor device includes a first memory cell including a first transistor and a second transistor, a second memory cell including a third transistor and a fourth transistor, and a driver circuit. The first transistor and the second transistor overlap at least partly with each other. The third transistor and the fourth transistor overlap at least partly with each other. The second memory cell is provided over the first memory cell. The first transistor includes a first semiconductor material. The second transistor, the third transistor, and the fourth transistor include a second semiconductor material.

The invention claimed is: 
     
       1. A semiconductor device comprising:
 a driver circuit; and 
 a circuit configured to be controlled by the driver circuit, 
 wherein the driver circuit comprises a first transistor having a first channel formation region comprising silicon, a second transistor having a second channel formation region comprising an oxide semiconductor, and a third transistor having a third channel formation region comprising the oxide semiconductor, 
 wherein the circuit comprises a fourth transistor having a fourth channel formation region comprising silicon and a fifth transistor having a fifth channel formation region comprising the oxide semiconductor, 
 wherein the fifth channel formation region is provided over the fourth channel formation region with an insulating layer provided therebetween, 
 wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, 
 wherein a gate of the second transistor is electrically connected to a gate of the third transistor, 
 wherein one of a source and a drain of the third transistor is electrically connected to a signal line, 
 wherein a gate of the fifth transistor and the signal line are electrically connected to each other, and 
 wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the fourth transistor. 
 
     
     
       2. The semiconductor device according to  claim 1 , wherein the insulating layer comprises a first layer comprising silicon oxide and a second layer comprising silicon nitride. 
     
     
       3. The semiconductor device according to  claim 1 , wherein the second transistor and the third transistor are provided over the first transistor. 
     
     
       4. The semiconductor device according to  claim 1 , wherein the first channel formation region and the fourth channel formation region are formed in a single crystal silicon substrate. 
     
     
       5. The semiconductor device according to  claim 1 , wherein the oxide semiconductor comprises indium, gallium, and zinc. 
     
     
       6. The semiconductor device according to  claim 1 , wherein the fourth transistor and the fifth transistor are included in a memory cell. 
     
     
       7. A semiconductor device comprising:
 a driver circuit; and 
 a circuit configured to be controlled by the driver circuit, 
 wherein the driver circuit comprises a first transistor having a first channel formation region comprising silicon, a second transistor having a second channel formation region comprising an oxide semiconductor, and a third transistor having a third channel formation region comprising the oxide semiconductor, 
 wherein the circuit comprises a fourth transistor having a fourth channel formation region comprising silicon, a fifth transistor having a fifth channel formation region comprising the oxide semiconductor, and a capacitor, 
 wherein the fifth channel formation region is provided over the fourth channel formation region with an insulating layer provided therebetween, 
 wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, 
 wherein a gate of the second transistor is electrically connected to a gate of the third transistor, 
 wherein one of a source and a drain of the third transistor is electrically connected to a signal line, 
 wherein a gate of the fifth transistor and the signal line are electrically connected to each other, 
 wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the fourth transistor, and 
 wherein the one of the source and the drain of the fifth transistor is electrically connected to a first electrode of the capacitor. 
 
     
     
       8. The semiconductor device according to  claim 7 , wherein the insulating layer comprises a first layer comprising silicon oxide and a second layer comprising silicon nitride. 
     
     
       9. The semiconductor device according to  claim 7 , wherein the second transistor and the third transistor are provided over the first transistor. 
     
     
       10. The semiconductor device according to  claim 7 , wherein the first channel formation region and the fourth channel formation region are formed in a single crystal silicon substrate. 
     
     
       11. The semiconductor device according to  claim 7 , wherein the oxide semiconductor comprises indium, gallium, and zinc. 
     
     
       12. The semiconductor device according to  claim 7 , wherein the fourth transistor and the fifth transistor are included in a memory cell. 
     
     
       13. A semiconductor device comprising:
 a driver circuit; and 
 a circuit configured to be controlled by the driver circuit, 
 wherein the driver circuit comprises a first transistor having a first channel formation region comprising silicon, a second transistor having a second channel formation region comprising an oxide semiconductor, and a third transistor having a third channel formation region comprising the oxide semiconductor, 
 wherein the circuit comprises a fourth transistor having a fourth channel formation region comprising silicon and a fifth transistor having a fifth channel formation region comprising the oxide semiconductor, 
 wherein the second transistor and the third transistor are provided over the first transistor, 
 wherein the fifth transistor is provided over the fourth transistor, 
 wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, 
 wherein a gate of the second transistor is electrically connected to a gate of the third transistor, 
 wherein one of a source and a drain of the third transistor is electrically connected to a signal line, 
 wherein a gate of the fifth transistor and the signal line are electrically connected to each other, and 
 wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the fourth transistor. 
 
     
     
       14. The semiconductor device according to  claim 13 , wherein the one of the source and the drain of the fifth transistor is electrically connected to a first electrode of a capacitor. 
     
     
       15. The semiconductor device according to  claim 13 , wherein the first channel formation region and the fourth channel formation region are formed in a single crystal silicon substrate. 
     
     
       16. The semiconductor device according to  claim 13 , wherein the oxide semiconductor comprises indium, gallium, and zinc. 
     
     
       17. The semiconductor device according to  claim 13 , wherein the fourth transistor and the fifth transistor are included in a memory cell.