Test device and test method thereof

Abstract

A test device method includes: setting a core voltage of a memory device to a first voltage value and a peripheral voltage of the memory device to a second voltage value; testing the memory device by accessing the memory device based on the core voltage and the at least one peripheral voltage; adjusting the core voltage to a third voltage value and the at least one peripheral voltage of the memory device to a fourth voltage value; testing the memory device by reading the memory device based on the core voltage and the at least one peripheral voltage; adjusting the core voltage to a fifth voltage value and the at least one peripheral voltage of the memory device to a sixth voltage value; and testing the memory device by reading the memory device based on the core voltage and the at least one peripheral voltage.

What is claimed is: 
     
       1. A test method for a memory device, comprising:
 setting a core voltage of a memory device to a first voltage value and at least one peripheral voltage of the memory device to a second voltage value; 
 testing the memory device by accessing the memory device based on the core voltage with the first voltage value and the at least one peripheral voltage with the second voltage value; 
 adjusting the core voltage to a third voltage value and the at least one peripheral voltage of the memory device to a fourth voltage value; 
 testing the memory device by reading the memory device based on the core voltage with the third voltage value and the at least one peripheral voltage with the fourth voltage value; 
 adjusting the core voltage to a fifth voltage value and the at least one peripheral voltage of the memory device to a sixth voltage value; and 
 testing the memory device by reading the memory device based on the core voltage with the fifth voltage value and the at least one peripheral voltage with the sixth voltage value, 
 wherein the third voltage value is smaller than the first voltage value, and the fourth voltage value is smaller than the second voltage value. 
 
     
     
       2. The test method according to  claim 1 , wherein the fifth voltage value is larger than the first voltage value. 
     
     
       3. The test method according to  claim 1 , wherein the sixth voltage value is larger than the second voltage value. 
     
     
       4. The test method according to  claim 1 , wherein the core voltage is smaller than the at least one peripheral voltage. 
     
     
       5. The test method according to  claim 1 , wherein a step of testing the memory device by accessing the memory device based on the core voltage with the first voltage value and the at least one peripheral voltage with the second voltage value comprises:
 writing at least one test pattern to all of a plurality of memory cells of a memory array of the memory device; 
 reading all of the plurality of memory cells of the memory array to obtain readout information; and 
 generating a test result by comparing the at least one test pattern with the readout information. 
 
     
     
       6. The test method according to  claim 1 , wherein a step of adjusting the core voltage to the third voltage value and the at least one peripheral voltage of the memory device to the fourth voltage value comprises:
 decreasing the core voltage from the first voltage by a first step voltage, and decreasing the at least one peripheral voltage from the second voltage by a second step voltage. 
 
     
     
       7. The test method according to  claim 6 , wherein each of the first step voltage and the second step voltage is between 5 millivolts to 10 millivolts. 
     
     
       8. The test method according to  claim 6 , wherein a step of adjusting the core voltage to the fifth voltage value and the at least one peripheral voltage of the memory device to the sixth voltage value comprises:
 increasing the core voltage from the third voltage by a third step voltage, and increasing the at least one peripheral voltage from the fourth voltage by a fourth step voltage. 
 
     
     
       9. The test method according to  claim 8 , wherein each of the third step voltage and the fourth step voltage is between 5 millivolts to 10 millivolts. 
     
     
       10. A test device for testing a memory device, comprising:
 a controller, coupled to the memory device, wherein the controller is configured to:
 set a core voltage of a memory device to a first voltage value and a peripheral voltage of the memory device to a second voltage value; 
 test the memory device by accessing the memory device based on the core voltage with the first voltage value and the at least one peripheral voltage with the second voltage value; 
 adjust the core voltage to a third voltage value and the at least one peripheral voltage of the memory device to a fourth voltage value; 
 test the memory device by reading the memory device based on the core voltage with the third voltage value and the at least one peripheral voltage with the fourth voltage value; 
 adjust the core voltage to a fifth voltage value and the at least one peripheral voltage of the memory device to a sixth voltage value; and 
 test the memory device by reading the memory device based on the core voltage with the fifth voltage value and the at least one peripheral voltage with the sixth voltage value, 
 
 wherein the third voltage value is smaller than the first voltage value, and the fourth voltage value is smaller than the second voltage value. 
 
     
     
       11. The test device according to  claim 10 , wherein the fifth voltage value is larger than the first voltage value. 
     
     
       12. The test device according to  claim 10 , wherein the sixth voltage value is larger than the second voltage value. 
     
     
       13. The test device according to  claim 10 , wherein the core voltage is smaller than the at least one peripheral voltage. 
     
     
       14. The test device according to  claim 10 , wherein the controller is further configured to:
 write a test pattern to all of a plurality of memory cells of a memory array of the memory device; 
 read all of the plurality of memory cells of a memory array to obtain readout information; and 
 generate a test result by comparing the at least one test pattern with the readout information. 
 
     
     
       15. The test device according to  claim 10 , wherein the controller is further configured to:
 decrease the core voltage from the first voltage by a first step voltage, and decreasing the at least one peripheral voltage from the second voltage by a second step voltage. 
 
     
     
       16. The test device according to  claim 15 , wherein the controller is further configured to:
 increase the core voltage from the third voltage by a third step voltage, and increasing the at least one peripheral voltage from the fourth voltage by a fourth step voltage. 
 
     
     
       17. The test device according to  claim 10 , further comprising:
 a voltage generator, coupled to controller, providing the core voltage and the at least one peripheral voltage. 
 
     
     
       18. The test device according to  claim 10 , further comprising:
 a test pattern provider, coupled to the controller, for providing the at least one test pattern.